M-core disables I210_SIUL1 via NVIC, which causes an A-core kernel panic.
When A-core debugs via the kernel command line using loglevel=7 debug, the kernel panic information is as follows:
[ 1977.361599] rcu: INFO: rcu_preempt detected expedited stalls on CPUs/tasks: { 0-... } 386566 jiffies s: 149 root: 0x1/. [ 1977.361638] rcu: blocking rcu_node structures (internal RCU debug): [ 1977.361643] Task dump for CPU 0: [ 1977.361646] task:swapper/0 state:R running task stack: 0 pid: 0 ppid: 0 flags:0x0000000a [ 1977.361658] Call trace: [ 1977.361660] __switch_to+0xf8/0x14c [ 1977.361679] 0x0 [ 1995.810781] systemd-journald[129]: Sent WATCHDOG=1 notification. [ 1998.853570] rcu: INFO: rcu_preempt self-detected stall on CPU [ 1998.853587] rcu: 0-....: (1 GPs behind) idle=54d/0/0x7 softirq=21933/21934 fqs=183681 [ 1998.853600] (t=462087 jiffies g=32685 q=77186) [ 1998.853605] Task dump for CPU 0: [ 1998.853609] task:swapper/0 state:R running task stack: 0 pid: 0 ppid: 0 flags:0x0000000a [ 1998.853624] Call trace: [ 1998.853626] dump_backtrace+0x0/0x1c0 [ 1998.853642] show_stack+0x18/0x40 [ 1998.853649] sched_show_task+0x168/0x19c [ 1998.853658] dump_cpu_task+0x44/0x58 [ 1998.853666] rcu_dump_cpu_stacks+0xe8/0x12c [ 1998.853673] rcu_sched_clock_irq+0x858/0xda0 [ 1998.853682] update_process_times+0x9c/0xf0 [ 1998.853689] tick_sched_timer+0x58/0xd0 [ 1998.853698] __hrtimer_run_queues+0x138/0x1d0 [ 1998.853706] hrtimer_interrupt+0xe8/0x244 [ 1998.853714] arch_timer_handler_virt+0x34/0x4c [ 1998.853724] handle_percpu_devid_irq+0x84/0x130 [ 1998.853735] handle_domain_irq+0x60/0x90 [ 1998.853745] gic_handle_irq+0x54/0x130 [ 1998.853752] do_interrupt_handler+0x34/0x60 [ 1998.853760] el1_interrupt+0x30/0x80 [ 1998.853768] el1h_64_irq_handler+0x18/0x2c [ 1998.853775] el1h_64_irq+0x78/0x7c [ 1998.853782] _stext+0x9c/0x274 [ 1998.853788] irq_exit+0x88/0xc4 [ 1998.853795] handle_domain_irq+0x64/0x90 [ 1998.853803] gic_handle_irq+0x54/0x130 [ 1998.853808] call_on_irq_stack+0x20/0x4c [ 1998.853814] do_interrupt_handler+0x54/0x60 [ 1998.853821] el1_interrupt+0x30/0x80 [ 1998.853827] el1h_64_irq_handler+0x18/0x2c [ 1998.853834] el1h_64_irq+0x78/0x7c [ 1998.853841] arch_cpu_idle+0x18/0x2c [ 1998.853849] do_idle+0xc4/0x150 [ 1998.853856] cpu_startup_entry+0x24/0x60 [ 1998.853862] rest_init+0xe0/0xf0 [ 1998.853867] arch_call_rest_init+0x10/0x1c [ 1998.853875] start_kernel+0x624/0x668 [ 1998.853882] __primary_switched+0xa0/0xa8
When loglevel=7 debug is not used, the kernel panic information is as follows:
[ 4008.606383] Unable to handle kernel paging request at virtual address 00000000003faa00 [ 4010.826820] Mem abort info: [ 4010.829560] ESR = 0x0000000086000005 [ 4010.833288] EC = 0x21: IABT (current EL), IL = 32 bits [ 4010.838589] SET = 0, FnV = 0 [ 4010.841614] EA = 0, S1PTW = 0 [ 4010.844737] FSC = 0x05: level 1 translation fault [ 4010.849599] user pgtable: 4k pages, 39-bit VAs, pgdp=000000088dbb8000 [ 4010.856026] [00000000003faa00] pgd=0000000000000000, p4d=0000000000000000, pud=0000000000000000 [ 4010.864711] Internal error: Oops: 0000000086000005 [#1] PREEMPT SMP [ 4010.864720] printk: console [ttyLF0]: printing thread stopped [ 4010.870948] Modules linked in: ipc_shm_uio(O) uio_hse pfeng(O) gpio_pca953x sja1110(O) mse102x [ 4010.885270] CPU: 0 PID: 12 Comm: ksoftirqd/0 Tainted: G O 5.15.145-rt73+g3a3fafb13baa+p0 #1 [ 4010.894902] Hardware name: Foxtron Fusion Domain Controller Gen 2 (XC1) (DT) [ 4010.901933] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 4010.908874] pc : 0x3faa00 [ 4010.911479] lr : vchan_complete+0xc0/0x234 [ 4010.915558] sp : ffffffc00901bc80 [ 4010.918856] x29: ffffffc00901bcc0 x28: 0000000000000020 x27: 0000000000000000 [ 4010.925973] x26: ffffff88000a6180 x25: ffffffc008bafa00 x24: ffffff885f85d680 [ 4010.933091] x23: 0000000000000002 x22: ffffffc00901bc90 x21: ffffff88008206f8 [ 4010.940209] x20: ffffff880d9b0858 x19: ffffff8800820658 x18: 0000000000000001 [ 4010.947327] x17: 0000000000000000 x16: 0000000000000000 x15: ffffffc00901b710 [ 4010.954444] x14: 0000000000000000 x13: 0000000000000001 x12: 0000000000000000 [ 4010.961561] x11: 0000000000000003 x10: 00000000000003c1 x9 : 0000000000000c00 [ 4010.968679] x8 : 000000000003d2e8 x7 : ffffffc008ca5188 x6 : ffffffc008ca5170 [ 4010.975797] x5 : 0000000000000000 x4 : 0000000000000000 x3 : ffffff88008206f8 [ 4010.982914] x2 : 00000000003faa00 x1 : ffffff880d9b0858 x0 : 0000000000000000 [ 4010.990033] Call trace: [ 4010.992465] 0x3faa00 [ 4010.994721] tasklet_action_common.constprop.0+0x124/0x150 [ 4011.000189] tasklet_action+0x28/0x34 [ 4011.003833] _stext+0x11c/0x274 [ 4011.006958] run_ksoftirqd+0x4c/0x60 [ 4011.010517] smpboot_thread_fn+0x234/0x260 [ 4011.014596] kthread+0x174/0x180 [ 4011.017808] ret_from_fork+0x10/0x20 [ 4011.021378] Code: bad PC value [ 4011.024410] ---[ end trace ab738991db2e3cd8 ]--- [ 4011.029098] Kernel panic - not syncing: [ 4011.032824] Oops: Fatal exception in interrupt [ 4011.032876] SMP: stopping secondary CPUs [ 4011.041162] Kernel Offset: disabled [ 4011.044630] CPU features: 0x8,00002001,20000842 [ 4011.049144] Memory Limit: none [ 4011.052183] ---[ end Kernel panic - not syncing: Oops: Fatal exception in interrupt ]---
Hi @alejandro_e
Our BSP is at version 40.0, and we are using kernel version 5.15 on the S32G3 platform. This setup is configured on a custom board with a boot type of QSPI, running multi-core where the A-core operates Linux and the M-core runs an RTOS. The debugger is set to the default configuration, and we use T32 to access the registers, as illustrated in the picture below.
The detailed dmesg information will be provided later.
I'm not sure how the NVIC register on the M core might affect the A core. Do you have any documentation that explains this?
Best regards,
Jeff Huang
Hello @Jeff-CF-Huang,
I have checked the related information of your problem, I was not able to find much information related to your problem. Can you share the lines in which the M7 is disabling the interrupt so I may look further into it?
The only relevant document I was able to find is in the S32G3_interrupt_map.xlsx attached with the reference manual:
You can see the following, it is an OR of all pin interrupts:
Can you give me more context about how and why are you disabling this interrupt in the M7?
Thanks
Hello @Jeff-CF-Huang,
To be able to support you better please provide the following information:
Thanks in advance for the information.