Is there an Emergency Stop mechanism for S32G?

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Is there an Emergency Stop mechanism for S32G?

509 Views
Icespring
Contributor I

For functional safety, sometimes we want to put certain external ports to high-impedance (or a trustable state), i.e. to shutoff CAN , when system fails. However in S32G series, I haven't seen similar configuration. I want to check if you have similar design, or we have to do external design by ourselves using the FCCU/FS0B. Thanks!

0 Kudos
Reply
3 Replies

484 Views
Miguel04
NXP TechSupport
NXP TechSupport

Hi @Icespring 

We understand that we do not provide specific driver or example for what you are proposing, sorry for the inconvenience. However, it is possible to configure the FCCU for this application under S32G2.

For example, the FCCU can generate a functional reset, which makes SIUL2 to go to default configurations, depending on the pin, the default configuration is almost always high impedance. All the resources available for the FCCU can be found on the reference manual chapter 67 Fault Collection and Control Unit (FCCU) Rev. 7, February 2023 and the pdf contains an attached file called fault map to distinguish all the NCF (Non critical faults).

I also can recommend looking into the Reset chapter 28, for more information of the module's states after a functional or destructive resets and the sources for each reset.

I apologize for the late reply, please let us know if you have more questions.

Best Regards, Miguel.

461 Views
Icespring
Contributor I
Hi Miguel!
Thanks for your reply! It really helps!
Furthermore, I want to check that when a reset is triggered by MC_RGM, will it FIRST set all the pins to their default state, THEN start the reset sequence? Is this order certain for all the reset?
Thanks!!
0 Kudos
Reply

445 Views
Miguel04
NXP TechSupport
NXP TechSupport

Hi @Icespring 

It seems that the information you are looking for can be found in figures 147 and 148 from the reference manual, these figures describes the sequence for functional and destructive resets with a flow diagram.

Miguel04_0-1701798116203.png

Miguel04_1-1701798143910.png

Let me know if you have any question.

Best Regards, Miguel.

 

0 Kudos
Reply