Initialization LPDDR on M7_0 core of S32G2

[harry_choi]

Hello Community,

I am trying to initialize LPDDR on M7_0 core of S32G2.

I generated ddr code on DDR tool on S32DS using S32 debug probe.

But when I just tried to write the generated configuration data on DDRC register, there was a fault like below:

*(volatile uint32 *)0x4007c604 = 0x00000000u;

What do I have to do before initialization DDR?

Could you let me know how I can initialize LPDDR on M7_0 core?

Thanks,

Harry

[alejandro_e]

Hello @harry_choi,

Can you tell me more about your setup?

• Are you using a RDB2 or a custom board?
• what is the part number of your memory? (in case you are using a custom board)
• What is the version of your RTDs?
• Are you using the A53 cores also? if so, which BSP are you using?
• When using DDR tool on S32DS, did it execute correctly?
• Does the application you are traying to run works fine until you get to the line you mentioned? ( *(volatile uint32 *)0x4007c604 = 0x00000000u; )

Thanks in advance for the information

[harry_choi]

Hi Alejandro,

Thanks for your reply.

Here are my answers.

- Are you using a RDB2 or a custom board? [Harry] custom board

- what is the part number of your memory? (in case you are using a custom board) [Harry] Samsung K4F6E3S4HM-THCL (2GB)

- What is the version of your RTDs? [Harry] It looks 4.0.0 

- Are you using the A53 cores also? if so, which BSP are you using? [Harry] not now, I will use A53 core later. I would like to initialize LPDDR on M7_0 core and it's customer's requirement.

- When using DDR tool on S32DS, did it execute correctly? [Harry] Yes, all tests were passed.

- Does the application you are traying to run works fine until you get to the line you mentioned? ( *(volatile uint32 *)0x4007c604 = 0x00000000u; ) [Harry] Yes, there was not problem. Just writing data on DDRC register 0x4007c606 caused this failure. As I know, writing 0x00000000u on 0x4007c604 register is the first step during ddr_init() function.

I already checked MPU enabled and those are both readable and writable area.

Thanks,

Harry

[alejandro_e]

Hello @harry_choi,

I will need to share this information with the  internal team for an in depth analysis. But before doing that I will need some extra information:

• The schematics of your design, at least the part including the S32G2 DRAM port and the LPDDR4 connections 
• LDDR4 datasheet
• Screenshots of the S32DS DDR View page, showing all the device information, code generation and advance settings sections
• Screenshots of the validation results of Init, Diags, Operational and Shmoo tests.

If you don't feel comfortable sharing this information in a public forum, please open a support case directly in the NXP page using this option:

To have better traceability of the topic you can add the link of this post in the body of the support ticket.

About the XRDC, You don't need to configure it to be able to initialize your ram.

Let me know how you want to proceed and thanks in advance for the information.

[harry_choi]

Hello Alejandro,

I think this problem is not related with the kind of DDR.

I would like to know why accessing below DDR_GPR register causes the connection failure to  S32 Debug probe.

I cannot read or write on DDR_GPR using S32 Debug probe like below:

I can access other registers. 

I think this is first problem.

Thanks,

Harry

[alejandro_e]

Hello @harry_choi,

Thanks for the clarification. How are configuring and initializing the DDR Clocks?

Thanks in advance for the information

[harry_choi]

Hello Alejandro,

Now I believe my problem is not related with DDR device.

Please focus on why I cannot access DDR_GPR register on M7_0 core.

Just accessing 0x4007C604 in DDR_GPR register caused bus error on JTAG.

Please check first accessing this address is prohibited or not.

Thanks,

Harry

[alejandro_e]

Hello @harry_choi,

I understand your problem is related with the DDR_GPR, but as described in the reference manual of the S32G2 [page 1692, S32G2 Reference Manual, Rev. 8, February 2024]

the DDR_GPR is meant as an extension of the DDR module. I have seeing this behavior of not being able to read the registers of a module when the clock of said module is not configured and initialized. 

Access is only prohibited if user mode is enable, M7 cores have supervisor mode by default, have you defined MCAL_ENABLE_USER_MODE_SUPPORT or have you enabled XRDC in your project?

Thanks in advance for the information.

[harry_choi]

Hello Alejandro,

It lools MCAN_ENABLE_USER_MODE_SUPPORT is not defined.

When I added below code in my source code and tried to compile, there was no build error.

#if defined(MCAL_ENABLE_USER_MODE_SUPPORT)
#error "MCAL USER MODE ENABLED"
#endif

Is it possible on your side to read the data in DDR_GPR register using T32?

Is it normal or not to try to read DDR_GPR register at entry?

Thanks,

Harry

[alejandro_e]

Hello @harry_choi,

No, I'm not able to read the DDR_GPR, but I'm using the S32 Debug probe. The aim of my questions was to gather information to share with the internal team. I will share all everything we have discussed with them and come back to you with an answer. Please consider that the internal team may have limited bandwidth and their response could take a while. I appreciate your patience.

Best regards,

Alejandro

[alejandro_e · Accepted solution]

Hello @harry_choi,

I have received feedback from the internal team, they shared the following:

"

Customer can refer to AN13354 for clock configuration details.

Actually we have the DDR init on M7 in Diagnostic test. You can get the code here:

Automotive SW - S32G - Board Diagnostic Tests

Note: this code is only for reference, not for product use.

Could you give me more information regarding how customer did the clock configuration, if possible can you ask customer provide the clock configuration file so we can review it?.

" 

Can you share your clock configuration so my colleague may review it?

If you cannot enter the link board diagnostic test directly please follow these steps:

- Sign in to your NXP account (NXP Semiconductors)

- Click on My NXP Account (top-right) and click on Software Licensing and Support under the Licensing section within the window it opens.

- This will redirect you to another page. In this new page, select the option View Accounts under the Software accounts section.

- This will again redirect you to another page. On this page, you should see an Automotive SW – S32G Reference Software option, click on it. and then search for Automotive SW - S32G - Board Diagnostic Tests, again, click on it.

- accept the Software Terms and Conditions, now you should be able to the file SW32G-DIAG-EAR-0.8.7.zip. 

If you cannot find some of the options in the FlexNet page, please follow up the point you can and then click on the direct link shared in the beginning. 

Let me know if this information solved your problem.

[harry_choi]

Hello Alejandro,

Thanks for your help.

Finally I succeeded to initialize DDR on M7_0 core.

Thanks,

Harry

[alejandro_e]

Hello @harry_choi,

I'm glad to know you were able to solve your problem. 

Thanks for selecting my reply as solution.

Best regards,

Alejandro 

[harry_choi]

In addition to this,

do I need more configuration like XRDC before accessing the DDR General Purpose Register  on M7_0 core?

I just initialized clock and MPU before accessing.

Thanks,

Harry