I2C timeout issue

[winstonlewis]

Hello,

We are using S32G399A chip on a customized board.

We are using 2 cores, out of the two cores, core 0 has only one partition and core 1 has two partitions.

We are using 3 I2C channels:

• Mapped I2C channel 4 to core 0.
• Mapped I2C channel 0 to ASIL partition of core 1.
• Mapped I2C channel 1 to QM partition of core 1.

Now when we are trying to access I2C channel 1, the channel always shows "I2C_IP_TIMEOUT_STATUS", other channels show "I2C_IP_SUCCESS_STATUS".

Could you please look into this issue.

We are using SW32G_RTD_4.4_4.0.2 version.

We are using the I2C channels on the M core side.

Regards,

Winston Lewis

[alejandro_e]

Hello @winstonlewis,

Thanks for reaching out to us and thanks for sharing all the relevant details of your problem.

Can you share a complete dump of the I2C registers from the three instances? this means a dump of the following ranges:

I2C_0: 0x401E_4000 - 0x401E_4006 

I2C_1: 0x401E_8000 - 0x401E_8006

I2C_4: 0x402D_C000 - 0x402D_C006

Can you also please check with an oscilloscope or logic analyzer if the devices you are using the I2C_1 are transmitting back to the S32G controller?

Thanks in advance

[winstonlewis]

Hello @alejandro_e , 

Thank you for the response.

Here is the dump of registers:

I2C_1:

I2C_1

I2C_4:

I2C_4

I2C_0:

Memory dump does not show any values.

I2C_0

When we probed the SDA and SCL lines on the oscilloscope, no I2C activity was observed; both lines remained constantly high.

Thanks & regards,

Winston Lewis

[alejandro_e]

Hello @winstonlewis,

Thanks for the information. I see that you have the same configuration for I2C_1 and I2C_4, although it is unusual that I2C_0 does not show the register values, since it is not the one with the problem, I will focus on I2C_1. When you mentioned the partitions, I assumed you meant RM/XRDC partitions, can you send screenshots of the configurations for the partition in M7_0 and for the M7_1?

Also, when were the registers dumps taken? For example, just after initialization or after sending a message.

Thanks in adavance

[winstonlewis]

Hello @alejandro_e ,

What I meant by partition was in core 1 we have two OS applications, one for ASIL and one for QM. We have assigned I2C 4 to ASIL application and I2C 1 for QM application and not RM/XRDC partitions.

Just wanted to understand which configuration screenshots are required.

The register dumps were taken after I2C went into timeout.

Thanks & regards,

Winston Lewis

[alejandro_e]

Hello @winstonlewis,

Thanks for the clarification, I understand now that you are doing SW partitions. Then I assume  you are using EcuC to create the partitions. If that is correct, please contact your software vendor, as for EcuC NXP does not provide any implementation, we only provide the stubs for the vendors to fill, my conclusion at the moment is that your QM partition does not have complete access to the memory sections needed for I2C_1. Also, checking the register values you shared, there seems to be no error in the module, in fact, it seems that the transfer was completed, I can see bit seven of  I2C Bus Status (IBSR) as 1.

Please let me know if my assumptions are correct.