How to rearrange and calculate port pin ID automatically with EB tresos

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How to rearrange and calculate port pin ID automatically with EB tresos

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StanleyShen
Contributor IV

Hi there

I am referring to the attached document to modify the bootloader,

just refer to the 3.4, could you tell me  know how to rearrange and calculate automatically port pin ID with EB tresos.

And as specified by the red circle, I am very confused about the new port ID, shouldn't the GPIO1_6_LED  be 41?

attach.png

And in my environment, there is no  SRE_3_3V_10MHZ can be chose,

Could you pls tell me the reason?

 

StanleyShen_0-1673260702985.png

 

Also, in section "3.5 Solve the clock conflict between Bootloader, MCAL and Linux",

Can you tell me what the words in different colors mean

StanleyShen_1-1673263062429.png

 

 

 

 

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Thanks for the information.

Seems odd, but still, for the input signal, SRE should not be a problem.

We could recommend using the 50MHz option, given this option should support faster frequencies.

Please, let us know.

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

What version of Tresos Studio and RTD are you using?

As for the 41, could be a typo, I have reproduced the example and it return an automatic 41. As for the SRE, I did have that option for the UART1_RX pin mentioned. Did you modified the Mscr field as specified?

SRE should not have an impact in an input pin, given it is more related to the output current and the higher the frequency, higher the current (we can say 50 MHz will have a faster rise/fall time than the 10 MHz option). Still, the option should be there.

FIRC_CLK is related to the internal clock source that S32G has available [Page 778, Chapter 23.2.4, S32G2 Reference Manual, Rev. 6, 11/2022]. FTM (FlexTimer) is a timer module [Page 1943, Chapter 43, S32G2 Reference Manual, Rev. 6, 11/2022]. FTM_x_REF_CLK is the source clock for the related FTM module.

Please, let us know.

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StanleyShen
Contributor IV

Hi

For the version information:

EB tresos 27.1.0

RTD_4.4_3.0.2_HF01_D2204

 

[As for the SRE, I did have that option for the UART1_RX pin mentioned. Did you modified the Mscr field as specified?]

As the next diagram, the Mscr is same to the reference  document.

StanleyShen_0-1673316438613.png

 

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Thanks for the information.

Seems odd, but still, for the input signal, SRE should not be a problem.

We could recommend using the 50MHz option, given this option should support faster frequencies.

Please, let us know.

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KeithWANG
Contributor II

As mentioned in the document, I did not find the example of Can_llc-pfe-th, may I ask where to get it, or what is the download link?

which is in the 2.4 Remove CLOCK INIT

Thanks!

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