How to configure Pfe2 with KSZ9031 using RGMII?

[harry_choi]

Hello Community,

I would like to enable pfe2 on my custom board.

Main soc is S32G274a and I am developing with bsp version 41.

KSZ9031 phy is connected pfe2 directly as same as S32G2-VNP-RDB2(Rev C2) but I cannot find any configuration enabling pfe2.

Could you let me know how to do ?

Thanks,

Harry

[chenyin_h]

Hello, @harry_choi 

Glad to hear that it works correct.

1. You may reference the doc/device-tree-bindings/net/phy.txt under u-boot for reference.

2. The error you mentioned seems a problem, since continous interrupt received.

BR

Chenyin

[chenyin_h]

Hello, @harry_choi 

For the RGMII_VDD, per my understanding, RGMII timing specification are valid for both 1.8 and 3.3V, but I would double check it if possible.

What is the mdio prints from your uboot? you may try if the mdio works fine with your PFE2 and KSZ connection, and to check the registers in PHY for further debugging.

Furthmore, would you please also share your full dts that related to your network setup?

BR

Chenyin

[harry_choi]

Hi Chenyin,

I didn't try to enable pfe2 on u-boot.

I attached s32gxxxa-rdb.dtsi.

I just changed the phy name and reg value.

diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
index 4a79bdb816bd..5fa32f3ea6fb 100644
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
@@ -51,9 +51,10 @@
};

&pfe_mdio2 {
+ reset-gpios = <&gpio 59 GPIO_ACTIVE_LOW>;
/* AR8035 */
- pfe_mdio_b_phy4: ethernet-phy@4 {
- reg = <4>;
+ pfe_mdio_b_phy3: ethernet-phy@3 {
+ reg = <3>;
};
/* SJA1110's phys: 0x09-0x0e */
};
@@ -72,7 +73,7 @@

&pfe_netif2 {
phy-mode = "rgmii-id";
- phy-handle = <&pfe_mdio_b_phy4>;
+ phy-handle = <&pfe_mdio_b_phy3>;
};

&generic_timer {

[harry_choi]

Hi Chenyin,

After I change the device tree in u-boot(actually in ATF), finally I succeeded to ping between my PC and board.

I think the kernel uses device tree in kernel source code(arch/arm64/boot/dts/freescale) but it looks u-boot device tree impacts to the RGMII.

I have two more questions.

1) how can I control reset pin of phy on u-boot? I used the property "reset-gpios" on kernel side but I cannot find any similar property in u-boot.

2) Below error message is not related with pfe2 operation? Can I disable the monitoring function by manual?

pfeng 46000000.pfe: ERR: (PFENG_NETDEV) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1283]

Thanks,

Harry

[chenyin_h]

Hi, @harry_choi 

Thanks for your reply.

I will check it further later, may I know if you have also tested the reverse side, ping from host to the board, could the data received by the phy?

BR

Chenyin

[harry_choi]

Hello Chenyin,

Of course, I doubled checked reverse side but there was no ping response from the board. 

Is not the interrupt pin on KSZ9031 to SoC required?

And also is not the 3.3V RGMII VDD related with this problem?

Thanks,

Harry

[harry_choi]

Hello Chenyin,

I attached the kernel log.

Could you look into the log?

After pfe initialization, below log printed out continuously.

[ 14.316490] pfeng 46000000.pfe: ERR: (PFENG_NETDEV) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1283]

Is it related with the pfe2 operation?

Thanks,

Harry

[harry_choi]

Hi Chenyin,

I already found the phy addr is 3, so after change reg value to <3>, phy attached to pfe2.

root@s32g274ardb2:~# ifconfig pfe2
pfe2 Link encap:Ethernet HWaddr 00:04:9F:BE:EF:02
inet addr:192.168.33.9 Bcast:192.168.33.255 Mask:255.255.255.0
inet6 addr: fe80::204:9fff:febe:ef02/64 Scope:Link
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:38 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:0 (0.0 B) TX bytes:6681 (6.5 KiB)
Memory:46000000-46ffffff

And the link was up (below is the result of "ethtool pfe2")

ethtool pfe2
Settings for pfe2:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Supported pause frame use: Symmetric
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Advertised pause frame use: Symmetric
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Link partner advertised pause frame use: Symmetric Receive-only
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 1000Mb/s
Duplex: Full
Auto-negotiation: on
master-slave cfg: preferred slave
master-slave status: slave
Port: Twisted Pair
PHYAD: 3
Transceiver: external
MDI-X: Unknown
Link detected: yes

But I still have problem.

When I try to run ping command, there is Destination Host Unreachable problem.

From 192.168.33.9 icmp_seq=22 Destination Host Unreachable
From 192.168.33.9 icmp_seq=23 Destination Host Unreachable
From 192.168.33.9 icmp_seq=24 Destination Host Unreachable

When I check the RGMII line, the clock was 125MHz (because the link connected with 1Gbps).

But all other lines (TXC, Data line) are all '0'.

What do you think the problem?

Thanks,

Harry

[chenyin_h]

Hello, @harry_choi 

Thanks for your reply.

Maybe you did not set correct phy addr of the phy you attached, which is the reg value you mentioned, would you confirm that it is 6 from your side? it depends on the board design and you may ask the HW engineer for the correct address to have a try.

BR

Chenyin

[harry_choi]

In my investigation, it looks phy devices are created and registered to the connected mdio(here, mdio2) when mdio is registered.

And when pfe2 is initialized, it searches the phy in the registered list and it attaches the found phy to the pfe interface. 

But, I believe there is no phys registered to mdio2 for pfe2.

In my case, when pfe2 is initialized, it cannot find phy and make an error.

So what I want to know is where or how phys are created and registered to the mdio2.

Thanks,

Harry

[harry_choi]

Hello Chenyin,

Thanks for your reply.

I added reset-gpios in the pfe_mdio2 to control reset pin of phy.

And also I added phy-handle with reg = <6> but I am not sure the reg value.

Could you let me know how I can know the phy reg value of KSZ9031?

&pfe_mdio2 {
  reset-gpios = <&gpio 59 GPIO_ACTIVE_LOW>;
  /* SJA1110's phys: 0x09-0x0e */
    gmac_mdio_a_phy6: ethernet-phy@6 {
    reg = <6>;
  };
};

&pfe_netif2 {
  phy-mode = "rgmii-id";
  phy-handle = <&gmac_mdio_a_phy6>;
};

In this case, the log shows it cannot find the phy as below.

[ 8.335989] pfeng 46000000.pfe: netif name: pfe2
[ 8.336006] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2
[ 8.336013] pfeng 46000000.pfe: netif(pfe2) mode: std
[ 8.336032] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04
[ 8.493049] pfeng 46000000.pfe pfe2 (uninitialized): Subscribe to HIF2
[ 8.493057] pfeng 46000000.pfe pfe2 (uninitialized): Host LLTX disabled
[ 8.493241] pfeng 46000000.pfe pfe2 (uninitialized): Enable HIF2
[ 8.493249] pfeng 46000000.pfe pfe2 (uninitialized): setting MAC addr: 00:04:9f:be:ef:02
[ 8.493286] pfeng 46000000.pfe pfe2 (uninitialized): PTP HW addend 0x80000000, max_adj configured to 46566128 ppb
[ 8.496015] pfeng 46000000.pfe pfe2 (uninitialized): Registered PTP HW clock successfully on EMAC2
[ 8.496060] device: 'pfe2': device_add
[ 8.496777] pfeng 46000000.pfe pfe2: registered
[ 8.669297] =====> /usr/src/debug/pfe/1.0.0-r0/git/sw/linux-pfeng/pfeng-phylink.c(355) netif_cfg name:pfe2, dn name:ethernet, full;ethernet@12
[ 8.669362] pfeng 46000000.pfe pfe2: ERR: (DRIVER) event 1 - Driver runtime error: [pfeng-phylink.c:358] could not attach PHY: -19
[ 8.669380] pfeng 46000000.pfe pfe2: ERR: (DRIVER) event 1 - Driver runtime error: [pfeng-netif.c:141] Error connecting to the phy: -19
root@s32g274ardb2:~# [ 45.363842] pfeng 46000000.pfe: ERR: (PFENG_NETDEV) event 42 - APP FSM timeout error: [pfe_emac_csr.c:1283]

Do you have any idea for the issue?

Thanks,

Harry

[chenyin_h]

Hello, @harry_choi 

Thanks for your post.

May I know your hwconfig in u-boot? since the phy used is the same with RDB2, I have checked the default settings on BSP41 with RDB2, PFE2 is by default enabled with default hwconfig.

root@s32g274ardb2:~# dmesg | grep pfe2
[ 7.789807] pfeng 46000000.pfe: netif name: pfe2
[ 7.789823] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2
[ 7.789829] pfeng 46000000.pfe: netif(pfe2) mode: std
[ 7.789846] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04
[ 7.974318] pfeng 46000000.pfe pfe2 (uninitialized): Subscribe to HIF2
[ 7.974328] pfeng 46000000.pfe pfe2 (uninitialized): Host LLTX disabled
[ 7.974515] pfeng 46000000.pfe pfe2 (uninitialized): Enable HIF2
[ 7.974524] pfeng 46000000.pfe pfe2 (uninitialized): setting MAC addr: 00:04:9f:be:ef:02
[ 7.974555] pfeng 46000000.pfe pfe2 (uninitialized): PTP HW addend 0x80000000, max_adj configured to 46566128 ppb
[ 7.975270] pfeng 46000000.pfe pfe2 (uninitialized): Registered PTP HW clock successfully on EMAC2
[ 7.976256] pfeng 46000000.pfe pfe2: registered
[ 9.772134] pfeng 46000000.pfe pfe2: PHY [pfeng-emac-2:04] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL)
[ 9.772164] pfeng 46000000.pfe pfe2: configuring for phy/rgmii-id link mode

BR

Chenyin

[harry_choi]

Hi Chenyin,

I believe there is a problem on RGMII interface between SoC and Phy chipset because there is no problem on link detection but there is no data on RGMII enable and data line.

Here is our HW design.

It is different on RGMII VDD compared with your reference board.

The reference board uses 1.8V by default but we designed to use 3.3V.

But I cannot find the problem now. 

Could you advise ?

Thanks,

Harry

[aaronbaranoff]

I have a similar issue in my case I don't get the RX clock coming from the phy. How did you resolve this issue?