How to change the pin config in u-boot?

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How to change the pin config in u-boot?

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ZeusChen
Contributor II

Hi NXP community,

Could I change a pin config form function pin to gpio using u-boot command?

For example: the FLEX_CAN_TXD (PB01) default is configured as function pin.

=> gpio status siul2-gpio017

Bank siul2-gpio0:

siul2-gpio017: func

Could I use u-boot command: "pinmux" to change it as a gpio pin?

If yes, what is the command format?

My platform is referenced S32G-VNP-RDB2.

BSP version: BSP_33.0

u-boot version: 2020.04

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

The "pinmux" command does not seem to be used for changing the SSS bit under the SIUL2.MSCRn register.

You should be able to "set" or "clear" a pin by using the "gpio" command, as shown below:

DanielAguirre_0-1689195519437.png

This command will set the OBE bit under the respective SIUL2.MSCRn register and set/clear the PDO_n bit under the SIUL2.GPDOn register.

This command will not change the SSS bit under the SIUL2.MSCRn. If you would like to modify this value you should be able to use the "mw.l" command, which will write a value of 32 bits to the defined address:

DanielAguirre_1-1689195851641.png

As seen on the above image, we changed the SSS bit for PA_06 (0x4009 C258) from 0x0 (GPIO[6]) to 0x2 (DSPI1_SOUT).

Please, let us know.

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1,798 次查看
Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

The "pinmux" command does not seem to be used for changing the SSS bit under the SIUL2.MSCRn register.

You should be able to "set" or "clear" a pin by using the "gpio" command, as shown below:

DanielAguirre_0-1689195519437.png

This command will set the OBE bit under the respective SIUL2.MSCRn register and set/clear the PDO_n bit under the SIUL2.GPDOn register.

This command will not change the SSS bit under the SIUL2.MSCRn. If you would like to modify this value you should be able to use the "mw.l" command, which will write a value of 32 bits to the defined address:

DanielAguirre_1-1689195851641.png

As seen on the above image, we changed the SSS bit for PA_06 (0x4009 C258) from 0x0 (GPIO[6]) to 0x2 (DSPI1_SOUT).

Please, let us know.

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