FlexRay test of S32G-VNP-RDB2

[Wanyj]

    I am testing the functionality of FlexRay using the FlexRay test of S32G-VNP-RDB2. I am using the sample program (Flexray_ExternalCommunication_node1_S32G274A_M7). It loops around pocState = Flexray_Ip_GetCurrentState(INST_FLEXRAY_0) while I debug; Medium. I wonder if this sample program or development board can test FlexRay.

    And if I want to use LLCE_FlexRay how do I test using S32G-VNP-RDB2，I hope someone can answer that. Thank you very much！

[Daniel-Aguirre]

Hi,

Which RTD/LLCE version are you using? How much nodes do you have on your FlexRay configuration?

As for LLCE-FR examples, we have the following information:

"FlexRay could not be tested on RBD2, the hardware did not connect to PHY.

Has been tested on S32G2 EVB, the function of flexray is ok."

Please, let us know.

[Wanyj]

Hi,

I am using the S32G_LLCE_1_0_5 and I only have the RDB2 development board.

Can't he be used for tests? Because I saw the port of LLCE_FR on his schematic,Looks like he should have all the way to LLCE FR.I want to know if I only have RDB2, how do I test it using the two ports shown here

Hope you can answer my doubts. Thank you very much.

[Daniel-Aguirre]

Hi,

FlexRay requires a minimum of 2 nodes to be able to be a valid network. Similar to CANBus, you cannot have a 1 node network, it will issue an Error (unless using internal loopback features).

As for RDB2, we understand that they have the available HW, but the example was not built for RDB2, but for EVB, as shown under the description.txt file:

That is why the comment "FlexRay could not be tested on RBD2, the hardware did not connect to PHY". If we see under the RDB2 schematic, the pins do not correspond with the example.

Please, let us know.

[Wanyj]

Hi， First of all thank you for your answer.Because the schematic diagram shows that RDB2's S32G274A chip has an "LLCE_FlexRay" interface connected to the transceiver TJA1081,I wonder if it is possible to use the LLCE_FlexRay port to send and receive FlexRay bus data by changing the port of the sample code,Or there's another way. Please, let me know.Thank you very much.

[Daniel-Aguirre]

Hi,

As for what it is available, there should be an FR example under the LLCE installation directory:

"C:\nxp\S32G_LLCE_1_0_5\plugins\eclipse\plugins\Fr_43_LLCE_TS_T40D11M10I5R0\examples\S32DS\S32G2"

Which should provide LLCE examples for FR. Still, those examples were verified with EVB platform.

You should be able to remap the pins, but you still require a 2nd node. Under RDB2, we understand that there is only 1 FR node.

Please, let us know.

[Wanyj]

Hi,

I know what you mean,Unfortunately, this sample code does not compile,His mistake is shown here,Also attached is my S32DS version.

I don't understand what went wrong. I didn't change any configuration. Did my software not match? Looking forward to your reply, thank you.

[Daniel-Aguirre]

Hi,

The errors you are showing seem to refer to a PATH not available. Can you confirm that the following PATH exists?

We understand that under your project, the folder does exist, but seems to be related to the project looking in another PATH, instead of your workplace. 

Is this happening with another example?

Please, let us know.

[Wanyj]

Hi,

Thanks for your reminding, now the project can compile successfully, but there is a new problem when I Debug.

I'm using a single step, and when I run the figure function, the program has an error and can't continue down.There was also a problem with his clock configuration (but the compilation didn't go wrong).

I don't understand what these two errors are. Do I need to change the default configuration? I look forward to your reply, thank you.

I put my project in the attachment, please check

[Daniel-Aguirre · Accepted solution]

Hi,

You should be able to modify the clock values to be inside the expected ranges:

As for the debug console error, this might be related to a debugger problem. Could be that the debugger is trying to access non-valid memory. 

Please, let us know.