Flash Tool S32 error wit target

[ARM_Kami]

Hi, 

I am getting error when I try to flash the system:

I get the same errors by the command line and the gui:

C:\WINDOWS\system32>C:\NXP\S32DS.3.5\S32DS\tools\S32FlashTool\bin\S32FlashTool -t c:\nxp\s32ds.3.5\S32DS\tools\S32FlashTool\targets\S32G2xxx.bin -fid -i uart -p COM10
Initializing Target.

Initializing Target.

Error: Target image load is failed!

Error: Failure to establish communication with target device.

I wonder if I need a different target.bin file.

There is Tx / Rx communication when I proceeed by JTAG s32 Debug Probe by the Flash tool remains saying failure to stablish communication with the target S32G274A Rev2

baud rate / bits /parity / control are they per default set by the Flash tool ? Are do I new to set up something else.

They board has a dip switch that set the serial Download and other dip switch that includes the JCOMP to allow the JTAG connection (miriac SBC-S32G274A)

Thank you in advance for your support.

Regards,

[carlos_o]

Hi @ARM_Kami, 

Thanks for your questions. 

I'm not familiar with the miriac board. Are you trying to load the code to the board with JTAG or with a serial COM? 

The error message you get can be the board is not initialized as Serial Boot. 

[ARM_Kami]

Hi, 

When the system tries to connect to the tartget I can see the message sent  in the Tx mentioned in the AN14136(page 7) but I don't see the echo in the Rx.

For UART non-secure serial boot:
At the association phase:
1. The transceiver sends a marker to BOOTROM with LINFlexD_0:
UART TX data: 0xFEEDFACECAFEBEEF
2. The transceiver receives an echoed message from BOOTROM with LINFlexD_0:
UART RX data: 0xFEEDFACECAFEBEEF

Sending after the Tx the message quoted before

I am not sure if the board has already the situation mentioned in the AN 13456 (page 5) "Serial boot is only available if the
DIS_SER_BOOT fuse bit is not blown". How can I verify this?

[ARM_Kami]

Hi,

I am trying by using the S32 Flash Tool.

By JTAG I can flash the system.

Just by Test connection I got the error:

Checking connection ...

Error: Failure to establish communication with target device.

I am using as target: S32G2xxx

even by command line I am getting the same error:

bin\S32FlashTool.exe -t targets\S32G2xxx.bin -ping -i uart -p COM10
Checking connection ...

Error: Failure to establish communication with target device.

I check all the combination of switches for the boot of this board.

I am getting the same errors.

[carlos_o]

Hi @ARM_Kami,

I understand, the most common cause of that issue is that the S32G is not setting to serial boot. 

The miriac SBC-S32G274A is a 3rd party product, so could you please ask to MircoSYS if they implement that boot option with the switches? 

[ARM_Kami]

I will check in that case with Microsys.

Please see the last post, and confirm my observation about no echo signal and how to verify the DIS_SER_BOOT fuse bit.

Thank you.

[carlos_o]

hi @ARM_Kami,

You refer to the AN14136(page 7) but that is a Bluetooth Direct Test Mode. 

About the DIS_SER_BOOT fuse, you can use the OCOTP module to read the fuses.

[page 3358, S32G2 Reference Manual, Rev. 8, February 2024] 

Something to remark is the 63.3.1.1 and 63.3.1.2 about the fuses

[page 3359, S32G2 Reference Manual, Rev. 8, February 2024]

For an example program you can check Ocotp_Ip_Example_S32G274A_M7 or Ocotp_Example_S32G274A_M7, for the RTD or MCAL/AUTOSAR API respectively. Please be careful when executing the code, as you know the fuses are one time programable.

If you have more questions about this topic, please let me know.

 

[ARM_Kami]

Please check the reference: Enabling Serial Boot in S32G page 7 as I mentioned originally.

[carlos_o]

Hi @ARM_Kami,

Regarding to the echo, the BootROM can't handle two consecutive bytes, so it should be checked echo after each byte, or insert in a small pause between the send bytes.

Were you able to confirm with Microsys if the Serial Boot was included as option with the switches? 

[ARM_Kami]

Hi, 

I was able to set the flashing configuration by pulling down by software one of the the balls in the microcontroller, even when the reference mentioned 2 of them.

I wonder, what is the maximum size of sw that I can flash in the NOR flash? If I need to take care of other details. The small examples are able to be flashed by this procedure but a 2.25 Mb is not able to be flashed.

Regards,

Hugo

[ARM_Kami]

Hi,

Thank you for the information!

The code that I am flashing is 2.25Mb, when this code is flashed by the S32 Debug Probe it works, when the same code is set in a SD card this also works, but when I flashed to the NOR flash it doesn't.

I followed the procedure described to prepare the _blob.bin file: 

-DCD file preparation (using an small UART example it works with and without the DCD bin file)

-IVT process: including (and not including) the DCD bin file; using the bin file from the application (adding the header: using the initial address (0x100 without DCD/ 0x130 with the DCD bin file) to generate a PreBlob file and  then generating the _blob.bin file to flash it by the IDE.

- The software doesn't run.

The application includes Ethernet connection, UART com, usin Free RTOS.

What steps am I missing? What extra configuration do I need to include in the flash process?

Observation:

- Small applications as the UART sending a Hello message works following the same process including and not the DCD file.

- the RAM start pointer / RAM entry pointer in the documentation use the same Address (in my case I use the RAM start pointer at 0x34000000 from the linker RAM file and for the RAM entry pointer the one in the map file for the *(.intc_vector)
.intc_vector 0x34207000 0x408 ./Project_Settings/Startup_Code/Vector_Table.o ); working for small examples.

Please:

- Is the DCD file neccessary? What extra config. is it neccessary?

- The RAM start pointer and RAM entry pointer what are the consideration to select them?

Regards,

Hugo

[carlos_o]

Hi @ARM_Kami,

The sw size limitations is not caused by the NOR Flash in this case, the boot process loads your sw into SRAM to run from there, so the limitation is given by the system RAM. This SRAM size will vary in the S32G model, this is mentioned as system RAM at the datasheet of the product.

[Page 5, S32G2 Data Sheet, Rev. 6, 12/2022]

The QSPI bus is mapped to can access up to an 512MB flash. 

Also, something else to consider is there is some peripherals that need use of the system RAM to run

1. PFE

Some SRAM was reserved for PFE by default in the device tree of BSP, show as the following:

You can change the default SRAM memory region to DDR.

2. LLCE

If you used the CAN2ETH or ETH2Can application for LLCE, then they need to notice some SRAM allocation in the applications, usually they are arrays and could check their SRAM address with debugger such as Lauterbach.

3. IPCF

The share SRAM memory (include local remote address and their size) could be configured, default configure shown as the following:

 

4. HSE

The memory map HSE could be found in attached S32G2_Memory_Map.xlsx, shown as the following:

5. eMMC boot

You need to find "Application boot image header" from IVT header and check its field "RAM start pointer" and "Code length" and know the location and size of your A53 application that loaded in SRAM. Make sure no overlapping between A53 and M7 application.

There's one more note about it:

 

Additional comments, you could check whether your application had been loaded in SRAM completely firstly through debugger or other viewer tool for memory.

Also, at 30.13.1 QuadSPI boot [S32G2 Reference Manual, Rev. 8, February 2024] the following is mentioned: 

[page 1255, S32G2 Reference Manual, Rev. 8, February 2024]

So, you need to ensure you application can be loaded in less than 500ms. 

Let me know if you have more questions. 

[ARM_Kami]

About the note in the Reference Manual (section 30.13.1.1): "... BootROM sets a timeout of 500ms when downloading the application image. User must ensure that the maximum image size can be downloaded within this time. The image size would depend on the configuration used."...

How can I verify that timeout?

Or do you have already a reference based on the code size?

Is the downloading of the application image the one from reset to load from  NOR flash into SRAM? Or from the serial flashing process?

[carlos_o]

Hi @ARM_Kami,

Q: Is the DCD file neccessary? What extra config. is it neccessary?

A: No, in this case the DCD is not necessary. Your config looks to be set properly, I would focus to verify first if the problem is from booting with QSPI with the 500 ms timeout. 

Q: The RAM start pointer and RAM entry pointer what are the consideration to select them?

A: At the .map file you can see the .intc_vector as you mentioned, this value indicates the location of the vector table. The RAM start pointer value can be found at the linker file as int_sram. This value refer to the memory map where is the start of the sram of the system.

Regarding to the 500ms timeout when downloading the application, it refers to the time when you reset the system and load from NOR flash into SRAM. If the image is too big and the trigger the timeout the system will reset (There is a reference code size, because it depends also in your QSPI because you can use HS200 or HS400). 

To verify if this is happening you can see if the reset signal is triggered. 

If is the case that you confirm that the error is happening by the timeout, an option can be to implement a bootloader you can see an example at the Application Note AN13750.

[ARM_Kami]

Hi Carlos,

Thank you for the information! 

Another question based in the last info: "it depends also in your QSPI because you can use HS200 or HS400... "

How can I correctly setup the config. for the QSPI?

Do I need to set up it by the DCD or other tool?

I see that the IVT can read a bin file for setting up the QSPI, How can I generate or get the correct file for this?

Is it the same file used for the algorithm when flashing the board by serial?

I see QSPI options for the DCD, where is the reference for these settings?

Thank you in advance for the information.

Regards!

[carlos_o]

Hi @ARM_Kami,

An apology, I confused the HS200/HS400 modes this is for eMMC.

The information you need for the QSPI boot configuration can be found in the following documents:

S32G Quad Serial Peripheral Interface (QSPI) Deep Dive

AN13563: S32G QuadSPI Deep Dive Application note

As you can see there is some reconfiguration parameters that has given with the S32 Design Studio.

Also, you can do your own reconfiguration thought the S32 Config Tool.

To do this Implementation the DCD is not necessary.