Hi Mr Daniel,
I use S32G-VNP-RDB2 eval board which has S32G274A chip and MX25UW51245G External Nor Flash.
I also use Mcal_S32x , SW32G_RTD_4.4_3.0.2_HF01 library. In this MCAL, I use FLS, FEE libraries " Fls_TS_T40D11M30I2R0 and Fee_TS_T40D11M30I2R0".
I use S32DS 3.5 IDE version.
When the platform is set to boot from RCON, I
I implement UART module for debugging to see which init phase goes timeout and then I found the call stack like :
Fls_Init()-> Fls_IPW_Init() -> Fls_IPW_InitMemories() -> Qspi_Ip_Init
In the Qspi_Ip_InitProtection function,
this status is returned as timeout "STATUS_QSPI_IP_TIMEOUT"
--> Before the proceeding get and set protection phase on flash , it ensures that the previous command is completed.
Previous command is came from Qspi_Ip_InitDevice function.
I mean before the Qspi_Ip_InitProtection function, Qspi_Ip_ControllerInit function is called. There are lots of QSPI operation handled in this function. After that Qspı_Ip_InitProtection function is called and in this function it waits until the previous command is completed. But it is not. It goes timeout.
When I run the platform on SRAM, it is initialized properly. However when I try to run on FLASH, it is not.
Could you please help me ?
Hi,
We may have missed if you said it or not, but have you used any of the available examples?
We are using the "Qspi_Ip_Example_S32G274A_M7" example which provides the following result (under SRAM):
It writes 128 bytes to the address 4096 decimal (0x1000) under the NOR Flash. We modified the example prior to flashing it to the S32G2-RDB2 platform, where the first value to be written is 2 instead of 0, then continue counting up (in other words, all values will have an offset of 2 decimal). Once we flash the example with this modification (using an IVT) we see the following outcome:
Which we correctly see the offset we provided to the example.
As a note, we obtain the Flash dump from S32 Flash Tool, we set the following range:
That is why the first address is 0x0 under our images.
In summary, we are not seeing the behavior you are seeing. As said in the beginning, are you using a provided example?
Please, let us know.
Hi
Thank you for your generosity in sharing such valuable insights and information.
Yes I used Qspi_Ip_Example_S32G274A_M7.
An update !
I noticed that, when I produce the blob image from binary, I select S32G274_QuadSPI_133MHz_SDR_configuration.
And once I flash the board, this problem occurs.
However when I select S32G274_QuadSPI_133MHz_DDR_configuration, the initialization phase is passed properly. Now I'm testing and trying to understand why.
Also the FLS configuration is the exactly the same as the example which you've mentioned Qspi_Ip_Example_S32G274A_M7.
Could you please help me to understand this ?
Best Regards,
Halil
Hi,
Could be a problem of the address where code is writing to. We have tried to use the SDR QSPI configuration and see no problem but moved the JOB_ADDRESS to 0x250000:
Since this address is not occupied by our application, it is not being erased, for which we need to erase this sector manually prior to executing the code.
Also, we modified the linker file as follows, for us to not use QSPI configuration to confirm the functionality without reconfiguration under the BootROM stage:
This same linker is used once we add the SDR configuration, we don't see any difference.
As for the configuration, should be, since we understand both provide the same functionality. Seems to us that the write address has changed, so it should be take into account.
Please, let us know.
