Access PFE MAC addresses via A53

[aaronbaranoff]

I am trying to talk to the PFE_MAC0 and 3 directly from the A53 (bare bones access). I was given the follow addresses and I am verifiying they are correct. The memory map in the reference manual seems to imply that they should be valid. I try to look at addresses via the debugger and before the MMU was enabled to verify I have the correct addresses.

PFE EMAC0 base - 0x460A0000

0x460A011C-0x460A0128

PFE EMAC1 base - 0x460A4000 

0x460A411C-0x460A4128

PFE EMAC2 base - 0x460A8000

0x460A811C-0x460A8128

I get nothing back (not even 0s). So, is the address you gave me valid for the A53 or do I need to enable something first to get access. What am I missing? Enables? Clocks?  

[aaronbaranoff · Accepted solution]

This sequence works to save the pain for the next person....

#define MAX_TRIES 100

void FSBL_pfe_init(void)

{

    /* Enable */

    /* Setup DMA coherency */

    volatile uint32_t tries;

    RDC.RD2_CTRL_REG.B.RD2_CTRL_UNLOCK = 1;

    RDC.RD2_CTRL_REG.B.RD2_INTERCONNECT_INTERFACE_DISABLE = 0;

    tries = 0;

    while (RDC.RD2_STAT_REG.B.RD2_INTERCONNECT_INTERFACE_DISABLE_REQ_ACK_STAT != 0 )

    {

        tries++;

        if (tries > MAX_TRIES)

        {

            break;

        }

    }

    tries = 0;

    while (RDC.RD2_STAT_REG.B.RD2_INTERCONNECT_INTERFACE_DISABLE_STAT != 0)

    {

        tries++;

        if (tries > MAX_TRIES)

        {

            break;

        }

    }

    /**((volatile unsigned int *)0x4007ca00) = 0x3f; */

    S32G_GPR.PFE_COH_EN.B.DDR = true;

    S32G_GPR.PFE_COH_EN.B.HIF0 = true;

    S32G_GPR.PFE_COH_EN.B.HIF1 = true;

    S32G_GPR.PFE_COH_EN.B.HIF2 = true;

    S32G_GPR.PFE_COH_EN.B.HIF3 = true;

    S32G_GPR.PFE_COH_EN.B.UTIL = true;

    /* Setup EMAC modes */

    /**((volatile unsigned int *)0x4007ca04) = 0x111;*/

    S32G_GPR.PFE_EMACX_INTF_SEL.B.EMAC0 = 1;

    S32G_GPR.PFE_EMACX_INTF_SEL.B.EMAC1 = 1;

    S32G_GPR.PFE_EMACX_INTF_SEL.B.EMAC2 = 1;

    /* Enable power for PFE */

    /**((volatile unsigned int *)0x4007ca20) = 0x0; */

    S32G_GPR.PFE_PWR_CTRL.B.PWRACK = 0;

    S32G_GPR.PFE_PWR_CTRL.B.PWRCLAMP = 0;

    S32G_GPR.PFE_PWR_CTRL.B.PWRDWN = 0;

    S32G_GPR.PFE_PWR_CTRL.B.PWRISO = 0;

    /* Put PFE in reset */

    /**((volatile unsigned int *)0x40078050) = 0x1; */

    MC_RGM.PRST_0[2].PRST_0.B.PERIPH_0_RST = 1;

    tries = 0;

    while (MC_RGM.PSTAT_0[2].PSTAT_0.B.PERIPH_0_STAT != 1)

    {

        tries++;

        if (tries > MAX_TRIES)

        {

            break;

        }

    }    

    /**((volatile unsigned int *)0x4007caE4) = 0x0; */

    S32G_GPR.GENCTRL1.B.CTRL = 0;

    /* Take the PFE out of reset */

    /**((volatile unsigned int *)0x40078050) = 0x0; */

    MC_RGM.PRST_0[2].PRST_0.B.PERIPH_0_RST = 0;

    MC_ME.PRTN2_PCONF.B.OSSE = 1;

    MC_ME.PRTN2_PCONF.B.PCE = 1;

    MC_ME.PRTN2_PUPD.B.OSSUD = 1;

    MC_ME.PRTN2_PUPD.B.PCUD = 1;

    /* Tell hardware to check above registers for changes */

    Write_Control_Key();

    tries = 0;

    while (MC_RGM.PSTAT_0[2].PSTAT_0.B.PERIPH_0_STAT != 0)

    {

        tries++;

        if (tries > MAX_TRIES)

        {

            break;

        }

    }

    /**((volatile unsigned int *)0x4007caE4) = 0x1; */

    S32G_GPR.GENCTRL1.B.CTRL = 1;

    /* Setup & Enable the PFE Sys Clock */

    /* See above clocking images */

    /* Setup and Enable the PFE PE Clock */

    /* *((volatile unsigned int *)0x4007ca44) = 0x0; */

    S32G_GPR.LLCE_CTRL.B.EXEVENT = 0;

    S32G_GPR.LLCE_CTRL.B.LINDIVSEL = 0;

    S32G_GPR.LLCE_CTRL.B.LLCE_HTM0_TRC_DIS = 0;

    S32G_GPR.LLCE_CTRL.B.LLCE_HTM1_TRC_DIS = 0;

    S32G_GPR.LLCE_CTRL.B.LLCE_LSPI_TRIG_IN = 0;

    S32G_GPR.LLCE_CTRL.B.PFE_2_LLCE_INT_HS_BP = 0;

    /* Take the PFE out of reset */

    /**((volatile unsigned int *)0x40078050) = 0x0; */

    MC_RGM.PRST_0[2].PRST_0.B.PERIPH_0_RST = 0;                  

    MC_ME.PRTN2_PCONF.B.OSSE = 1;

    MC_ME.PRTN2_PCONF.B.PCE = 1;

    MC_ME.PRTN2_PUPD.B.OSSUD = 1;

    MC_ME.PRTN2_PUPD.B.PCUD = 1;

    /* Tell hardware to check above registers for changes */

    Write_Control_Key();

    tries = 0;

    while (MC_RGM.PSTAT_0[2].PSTAT_0.B.PERIPH_0_STAT != 0)

    {

        tries++;

        if (tries > MAX_TRIES)

        {

            break;

        }

    }

    MC_ME.PRTN2_PCONF.B.OSSE = 0;

    MC_ME.PRTN2_PCONF.B.PCE = 1;

    MC_ME.PRTN2_PUPD.B.OSSUD = 1;

    MC_ME.PRTN2_PUPD.B.PCUD = 1;

    /* Tell hardware to check above registers for changes */

    Write_Control_Key();

    tries = 0;

    while (MC_RGM.PSTAT_0[2].PSTAT_0.B.PERIPH_0_STAT != 0)

    {

        tries++;

        if (tries > MAX_TRIES)

        {

            break;

        }        

    }

    /**((volatile unsigned int *)0x4007caE4) = 0x1; */

    S32G_GPR.GENCTRL1.B.CTRL = 1;

    /* Setup EMAC Tx/RX clocks */

    /* *((volatile unsigned int *)0x4007caE0) = 0x0; */

    S32G_GPR.GENCTRL0.B.ACCEL_FLXNC_RD0_IDLEREQ = 0; /* normal operation */

    S32G_GPR.GENCTRL0.B.ACCEL_FLXNC_REF_DIV = 0; /* Divide by 2 */

    S32G_GPR.GENCTRL0.B.USBPWRFLT = 0;    

}

After the above code is running I can read and write to all the PFE GMACs,,,

PFE EMAC0 base - 0x460A0000

0x460A011C-0x460A0128

PFE EMAC1 base - 0x460A4000 

0x460A411C-0x460A4128

PFE EMAC2 base - 0x460A8000

0x460A811C-0x460A8128

[alejandro_e]

Hello @aaronbaranoff,

Thanks a lot for sharing your solution. I have received information from the internal team, please check the following sections of the S32G2 reference manual [S32G2 Reference Manual, Rev. 8, February 2024]:

• 28.12.4 Software reset partition turn-on flowchart
• 28.12.7 PFE software reset partition turn-on flowchart
• 23.1.2.7 Other clocks
  • 23.1.2.7.1 PFE_MAC_0 clocking overview
  • 23.1.2.7.2 PFE_MAC_1 clocking overview
  • 23.1.2.7.3 PFE_MAC_2 clocking overview

I apologize for the late solution, I was not aware of that information in the reference manual.

Since you already selected an answer as a solution, if you have more questions please create a new post in this community.

Thanks

[aaronbaranoff]

Here is a specific question address 0x40078050 after I have taken it out of reset read 0x1fe (lsb is 0 as expected). But 0x40078150 the status is 0x1ff (lsb is showing the PFE is still in reset). So the Peripheral Reset show it is out of reset but the status shows it is still in reset. Why? 

My clocks for the PFE are at defaults.

[alejandro_e]

Hello @aaronbaranoff,

I checked the code of pfeng, Linux and PFE MCAL and I have found nothing relevant regarding your problem. I will share this topic with the internal team for better support, this may take a while depending on their workload. If possible during that time, please check the examples I mentioned in the FCI manual and monitor these registers.

Is this causing any other problem? this is, any functional problem? other than interfering with the logic of your implementation.

Thanks in advance for your patience.

[aaronbaranoff]

This is my latest sequence (does not work yet) but, I think I am close. Please take a look and see if I am missing anything...

    /* Setup DMA coherency */

    /**((volatile unsigned int *)0x4007ca00) = 0x3f; */

    S32G_GPR.PFE_COH_EN.B.DDR = true;

    S32G_GPR.PFE_COH_EN.B.HIF0 = true;

    S32G_GPR.PFE_COH_EN.B.HIF1 = true;

    S32G_GPR.PFE_COH_EN.B.HIF2 = true;

    S32G_GPR.PFE_COH_EN.B.HIF3 = true;

    S32G_GPR.PFE_COH_EN.B.UTIL = true;

    /* Setup EMAC modes */

    /**((volatile unsigned int *)0x4007ca04) = 0x111;*/

    S32G_GPR.PFE_EMACX_INTF_SEL.B.EMAC0 = 1;

    S32G_GPR.PFE_EMACX_INTF_SEL.B.EMAC1 = 1;

    S32G_GPR.PFE_EMACX_INTF_SEL.B.EMAC2 = 1;

    /* Enable power for PFE */

    /**((volatile unsigned int *)0x4007ca20) = 0x0; */

    S32G_GPR.PFE_PWR_CTRL.B.PWRACK = 0;

    S32G_GPR.PFE_PWR_CTRL.B.PWRCLAMP = 0;

    S32G_GPR.PFE_PWR_CTRL.B.PWRDWN = 0;

    S32G_GPR.PFE_PWR_CTRL.B.PWRISO = 0;

    /* Put PFE in reset */

    /**((volatile unsigned int *)0x40078050) = 0x1; */

    MC_RGM.PRST_0[2].PRST_0.B.PERIPH_0_RST = 1;

    /**((volatile unsigned int *)0x4007caE4) = 0x0; */

    S32G_GPR.GENCTRL1.B.CTRL = 0;

    /* Take the PFE out of reset */

    /**((volatile unsigned int *)0x40078050) = 0x0; */

    MC_RGM.PRST_0[2].PRST_0.B.PERIPH_0_RST = 0;

    /**((volatile unsigned int *)0x4007caE4) = 0x1; */

    S32G_GPR.GENCTRL1.B.CTRL = 1;

    /* Setup & Enable the PFE Sys Clock */

    /* See above clocking images */

    /* Setup and Enable the PFE PE Clock */

    /* *((volatile unsigned int *)0x4007ca44) = 0x0; */

    S32G_GPR.LLCE_CTRL.B.EXEVENT = 0;

    S32G_GPR.LLCE_CTRL.B.LINDIVSEL = 0;

    S32G_GPR.LLCE_CTRL.B.LLCE_HTM0_TRC_DIS = 0;

    S32G_GPR.LLCE_CTRL.B.LLCE_HTM1_TRC_DIS = 0;

    S32G_GPR.LLCE_CTRL.B.LLCE_LSPI_TRIG_IN = 0;

    S32G_GPR.LLCE_CTRL.B.PFE_2_LLCE_INT_HS_BP = 0;

    /* Take the PFE out of reset */

    /**((volatile unsigned int *)0x40078050) = 0x0; */

    MC_RGM.PRST_0[2].PRST_0.B.PERIPH_0_RST = 0;

    /**((volatile unsigned int *)0x4007caE4) = 0x1; */

    S32G_GPR.GENCTRL1.B.CTRL = 1;

    /* Setup EMAC Tx/RX clocks */

    /* *((volatile unsigned int *)0x4007caE0) = 0x0; */

    S32G_GPR.GENCTRL0.B.ACCEL_FLXNC_RD0_IDLEREQ = 0; /* normal operation */

    S32G_GPR.GENCTRL0.B.ACCEL_FLXNC_REF_DIV = 0; /* Divide by 2 */

    S32G_GPR.GENCTRL0.B.USBPWRFLT = 0;    

Verifying this is correct while trying to read the addresses below.

After that read memory…

PFE EMAC0 base - 0x460A0000

0x460A011C-0x460A0128

PFE EMAC1 base - 0x460A4000 

0x460A411C-0x460A4128

PFE EMAC2 base - 0x460A8000

0x460A811C-0x460A8128

[alejandro_e]

Hello @aaronbaranoff,

Sorry for the late reply. Although I can help you with specific problem you may encounter during your development process, it is outside of the scope of the support we to guide you in your own implementation. As you already know we already offer some implementation, from my perspective the best is to use the FCI (Fast Control Interface), you can get the document from the PFE MCAL package I helped you get in previous tickets.

The FCI API Reference includes many examples on how to implement different use cases, such as: demo feature physical interface, demo feature L2 bridge vlan, demo feature router simple, and many more, please check section 18 Examples. Although it is in a somewhat inconvenient format, you just need to copy and paste the C code in the pdf into a .c file and it should work. You can get the init sequence from any of the demos.

You will need to check the following sections for all the details on the API:

• 12 Commands
• 13 Events
• 14 Functions
• 15 Structs
• 16 Enums
• 17 Miscellaneous symbols

All the code in those sections is already in header or source files in the PFE MCAL package.

To get the best support I would not recommend using PFE in a entirely bare-metal project, using the FCI API, in particular in the A53, should not cause a noticeable overhead and it comes with the advantage that it is a tested API.

Please let me know if you encounter any problem when using the examples

[aaronbaranoff]

This is my latest...

Clocking needs (not all instantly but eventually).

#define PFE_CLK_SYS_RATE 300000000

Therefore PFE_PE_CLK should be 600000000

From my continuing efforts... 

• Setup DMA coherency
  *((volatile uint32 *)0x4007ca00) = 0x3f;

• Setup EMAC modes
  *((volatile uint32 *)0x4007ca04) = 0x111;

• Enable power for PFE
  *((volatile uint32 *)0x4007ca20) = 0x0;

• Put PFE in reset
  *((volatile uint32 *)0x40078150) = 0x1;
  *((volatile uint32 *)0x4007caE4) = 0x0;

• Take the PFE out of reset
  *((volatile uint32 *)0x40078150) = 0x0;
  *((volatile uint32 *)0x4007caE4) = 0x1;

• Setup & Enable the PFE Sys Clock
  See above clocking images

• Setup the PFE PE Clock
  *((volatile uint32 *)0x4007ca44) = 0x0;

• Enable the PFE PE Clock
  *((volatile uint32 *)0x4007ca44) = 0x0;

• Take the PFE out of reset
  *((volatile uint32 *)0x40078150) = 0x0;
  *((volatile uint32 *)0x4007caE4) = 0x1;

• Setup EMAC Tx/RX clocks
  *((volatile uint32 *)0x4007caE0) = 0x0;

• Setup PFE PTP clock (not needed I believe)

Does this look correct? The PFE Sys I am not sure of the registers needed to setup the clock yet and I am not sure I am making the correct choices for the reset control and if the PTP clock is even needed in our mode. Any missing steps or order? This is all before I can talk to the PFE GMAC registers, correct?

[aaronbaranoff]

One more update...

Clocking needs (not all instantly but eventually).

#define PFE_CLK_SYS_RATE 300000000

Therefore PFE_PE_CLK should be 600000000

From my continuing efforts... 

• Setup DMA coherency
  *((volatile uint32 *)0x4007ca00) = 0x3f;

• Setup EMAC modes
  *((volatile uint32 *)0x4007ca04) = 0x111;

• Enable power for PFE
  *((volatile uint32 *)0x4007ca20) = 0x0;

• Put PFE in reset
  *((volatile uint32 *)0x4007caE4) = 0x1;

• Take the PFE out of reset
  *((volatile uint32 *)0x4007caE4) = 0x0;

• Setup & Enable the PFE Sys Clock
  See above clocking images

• Setup the PFE PE Clock
  *((volatile uint32 *)0x4007ca44) = 0x0;

• Enable the PFE PE Clock
  *((volatile uint32 *)0x4007ca44) = 0x0;

• Take the PFE out of reset
  *((volatile uint32 *)0x4007caE4) = 0x1;

• Setup EMAC Tx/RX clocks
  *((volatile uint32 *)0x4007caE0) = 0x0;

• Setup PFE PTP clock (not needed I believe)

Does this look correct? The PFE Sys I am not sure of the registers needed to setup the clock yet and I am not sure I am making the correct choices for the reset control and if the PTP clock is even needed in our mode, Any missing steps or order? This is all before I can talk to the PFE GMAC registers correct?

[alejandro_e]

Hello @aaronbaranoff, 

Thanks for contacting us again and sorry for the late reply.

Regarding your problem, do you mena that you cannot read any of the address space for the three PFE EMACs? this is, from 0x00 to 0x136C for all three base addresses. 

if you are not performing any kind of initialization nor clock configuration you can check how it is done in the Linux library we offer, you can start where the driver gets probed pfeng-drv.c#L359.

You can also flash one of the precompiled Linux BSP we offer (since they include the PFE FW), stop the boot in u-boot and then dump the memory for the interested ranges with the md command, this way you can check the statuses of the registers after the initialization of the PFE emacs.

Please also check the BSP user manual and PFE documentation available in the same FlexNet page in which you can download the binaries.

Let me know if you have more questions.

[aaronbaranoff]

I need the devicetree for linux for be to follow the code. Where can I find that?

Looks like I need to take out of reset and power up the interface and setup the clock (although problay not for the register interface). However to determine the addresses I need the devicetree that defines the reset and power up addresses.

I don't seem to have the devicetree for the S32G2. Remember we are not using u-boot or linix so, I just using them as a guide.

Simply, I might dump the registers if I knew which ones to dump. But, the linux driver refers to the devicetree that I pretty sure I don't have I can't find 

"pfe_sys"

"pfe_part"

"pfe_pe"

...

Even better, would be If there was a register definition and sequence documented for the PFE GMAC bring ups.

Aaron

[alejandro_e]

Hello @aaronbaranoff,

I apologize but the PFE documentation is not public and I have no control over that decision.

You are correct, the device tree node is not present in the pfen repo, it is present in the Linux repo, here is the link: /arch/arm64/boot/dts/freescale/s32g-pfe.dtsi.

I am aware that your are not using Linux nor u-boot, however, I can only refer to those in my recommendations as that is what we officially support.

Let me know if you have more questions

[aaronbaranoff]

I realize it is not you personally. It just seems bizzare and bad choice and slows our progress that the documention is not public (or behind a simple NDA or similiar). Instead I have to extract it from linux source which is not always the most straight forward way to do things. I am thinking we are not the 1st to do this. I was hoping there was a better way or someone else has done this before.

Until then I have just pulled the sources linux down so can do this.

From the probe I have the following to do (after I reverse engineer the addresses and the bits)...

• Enable power for PFE
• Put PFE in reset 
• Setup the PFE Sys Clock
• Enable the PFE Sys Clock
• Setup the PFE PE Clock
• Enable the PFE PE Clock
• Take the PFE out of reset
• Setup  EMAC Tx/RX clocks
• Setup PFE PTP clock

Does this look correct? Any missing steps or order?

The addresses seems they start at 0x46000000. I have written device tree info for linux but going from a device tree back the other direction is an ugly process. 

By the way we do have NDAs with NXP if that helps. 

Aaron 

[aaronbaranoff]

From my continuing efforts... 

• Setup DMA coherency
  *((volatile uint32 *)0x4007ca00) = 0x3f;

• Setup EMAC modes
  *((volatile uint32 *)0x4007ca04) = 0x111;

• Enable power for PFE
  *((volatile uint32 *)0x4007ca20) = 0x0;

• Put PFE in reset 
  *((volatile uint32 *)0x4007caE4) = 0x0;
• Take the PFE out of reset
  *((volatile uint32 *)0x4007caE4) = 0x1;

• Setup the PFE Sys Clock
• Enable the PFE Sys Clock
• Setup the PFE PE Clock

*((volatile uint32 *)0x4007ca44) = 0x0;

• Enable the PFE PE Clock

*((volatile uint32 *)0x4007ca44) = 0x0;

• Take the PFE out of reset

*((volatile uint32 *)0x4007caE4) = 0x1;

• Setup  EMAC Tx/RX clocks

*((volatile uint32 *)0x4007caE0) = 0x0;

• Setup PFE PTP clock

Does this look correct? The PFE Sys I am not sure of the registers needed to setup the clock yet and I am not sure I am making the correct choices for the reset control and if the PTP clock is even needed in our mode, Any missing steps or order? This is all before I can talk to the PFE GMAC registers correct?