Hi NXP community,
I have a problem with the LPSPI0 transfers which explain below.
When I set LPSPI0 as master to transmit 4 bytes at 4,8MBaudrate with LPSPI0_CLK_SEL = 24MHz (FIRCDIV2 / 2), there seems to be a pause in the middle of the 4 bytes I’m sending.
The applied settings can be seen in the following images.
To isolate the problem as much as possible I have done a project that only sets LPSPI0 as master and makes an infinite loop that only makes transmissions and waits.
If you need to clarify anything about the management or configuration I do in the LPSPI interface, please let me know.
Best regards,
Hello @FBS,
If you configure the SDK LPSPI for 8bit frames, in the interrupt mode, the LPSPI_DRV_FillupTxBuffer() function (lpspi_shared_function.c) that is called from the interrupt handler can fill the TX FIFO with 8bit frames. The FIFO can take only up to 4 such frames.
The SDK LPSPI driver needs some time to fill the TX FIFO (CPU overhead).
You can reduce the delay either by increasing the system clock frequency or by reducing the SPI bitrate.
Regards,
Daniel
