S32 design studio demo project[ FLASH_Example] issue

[喀秋莎]

I imported a demo that  is Flash_Example for the S32k144 board. And the demo comple is OK.

Running result is correct. But after changing clock (from Fast IRC to system PLL ), it doesn't run  normally.

I expect that the project always run if using OSC.

Figure 1

modifing demo Default clock Source  :Fast IRC,  Configuring Flash Clock Source  :System PLL

 After starting  project ,No running normally

what is more,This reference manual of  S32K144RM reports Flash Clock is from FLASH_CLK,  However, 

when Rrocessor Expert configures Flash Clock, Flash Clock is from BUS_CLK ?

Figure 2

clocking architecture and various clock
sources for S32K144 demoboard.

Configuring Flash Clock : 8MHz   ,Bus Clock  :24MHz

However,In PCC Clock,how Flash Clock is 24MHz ?

hoping  resolve,In a hurry.

 thanks a lot

Original Attachment has been moved to: Figure-2.rar

Original Attachment has been moved to: Figure-1.rar

[raresvasile]

Hi,

I am working at S32 SDK and I can help you but first I need to ask you a few questions to be able to reproduce your issues.

1) What version of S32 Design Studio are you using? You can find the version number and build id under Help -> About S32 Design Studio.

2) Can you provide me the version number of the S32 SDK? Please look at Window -> Preferences -> SDK Management, there you will find the version on the next tab following S32K144_SDK_gcc.

Now, regarding the FLASH clock.

The S32K144 features two types of clocking for the modules:

   - Interface clock - is the clock that ensures the functionality of the module's registers and internal state machine. This clock appears in the PCC tab. In the case of the FLASH module the Interface clock is the BUS Clock (please see the table attached), this is why modifying the FLASH clock in the SCG tab did not affect the clock for the module. Underneath is the picture you had attached in the original post, but I have highlighted the Interface clock column for you to better understand the previous explanation. 

   - Functional clock - this is the clock source that feeds the logic of the modules( eg. clock source for the LPUART (eg. shifters) and it is configurable to allow asynchronous operations in respect to the main clock sources and CPU state, for example: using a timer module when the CPU is in sleep mode and all most of the clock sources are off. In the case of the FLASH module it is programmed from the SCG module in the Slow Divider Field. The manual states that: "FLASH_CLK frequency must be programmed to 28 MHz or less in HSRUN, 26.67 MHz or less in RUN, and an integer divide of the CORE_CLK. The core clock to flash clock ratio is limited to a max value of 8.".

Thank you for your feedback, it is really appreciated.

I am waiting for the answer to my questions so I will be able to help you.

Best regards,

Rares Vasile