I am porting some existing (and probably long time working) code for SPC5645C (e200z0, e200z4) from Diab Compiler to S32DS_Power_Win32_v2017.R1_b171019
In the startup code I am struggling with the e_cmpwi instruction:
/* Check length of SRAM data in ROM */
ASM2ID(e_cmpwi r9, 0);
/* Exit cfg_ROMCPY if size is zero */
366 ???? 7120E000 e_lis 9,__ROM_COPY_SIZE@ha
367 ???? 1D290000 e_add16i 9,9,__ROM_COPY_SIZE@l
368 ???? 1820A800 e_cmpwi 9,0
**** Error: operand out of range (9 is not between 0 and 3)
**** Error: missing operand
369 ???? 4182002C beq _ram_copy_end
In EREF_RM the register value occupies 5 bits of the opcode and I could not find any constraint for register rA to be in the range 0...3. Also there is no "missing operand", so I feel quite confident that this is a bug.
Thats really not a bug.
You are using e_cmpwi mnemonic which is actually just an alias. There is no such instruction in PowerISA document.
Meaning of this alias was recently changed in binutils mainline.
See also compiler release notes chapter 3.2:
Opcodes and syntax for e_cmpwi and e_cmplwi aliases were changed. Use e_cmpl16i instead of e_cmplwi, and e_cmp16i instead of e_cmpwi.
I had already -Wa,-mregnames turned on and switched to Alex's suggestion which compiled fine:
__asm("e_cmp16i r9,0"); 277 0262 70099800 e_cmp16i r9,0
By the way, is there a common way to access all the SPRs by symbolic name other than:
.set l1csr1, 1011 mtspr l1csr1, r5
Thanks for the report! This is indeed a GCC VLE compiler bug.
I reported this into our defect tracking database under CMPE200GCC-182.
I'd recommend you to use direct instruction opcode as a workaround.
asm(".long 0x70099800"); 70 09 98 00 e_cmp16i r9,0