S32DS's equivalent of CW compiler's directive?

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S32DS's equivalent of CW compiler's directive?

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Contributor III

What would be the S32DS's  equivalent of CW's compiler "__declspec(interrupt SRR)"?

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3 Replies

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NXP Employee
NXP Employee

Hello David,

I'm afraid that this target-specific attribute is not supported by GCC for PowerPC back-end.

I'd recommend you to create an equivalent interrupt handler in assembler ( see below the example of the default IVOR4 implementation - "intc_sw_handlers.s" from the default project generated in S32DS). You will need to add the instruction to save/restore  SRR registers.

.globl   Z7_1_IVOR4_Handler
    
#ifdef __ghs__
    .section    .vletext, axv
    .vle
#endif

    .equ  INTC_IACKR, 0xFFF48014  ;# Interrupt Acknowledge Register address
    .equ  INTC_EOIR,  0xFFF4801C   ;# End Of Interrupt Register address

    .align 4

Z7_1_IVOR4_Handler:
prologue:
    e_stwu      r1,-0x50 (r1)           ;# Create stack frame and store back chain
    e_stmvsrrw      0x0c (r1)           ;# Save SRR[0-1] (must be done before enabling MSR[EE])
    se_stw      r3, 0x08 (r1)           ;# Save working register (r3)
    e_lis       r3, INTC_IACKR@ha       ;# Save address  of INTC_IACKR in r3
    e_lwz       r3, INTC_IACKR@l(r3)    ;# Save contents of INTC_IACKR in r3 (this is vector table address)
    wrteei      1                       ;# Set MSR[EE] (must wait a couple clocks after reading IACKR)
    se_lwz      r3, 0x0(r3)             ;# Read ISR address from Interrupt Vector Table using pointer
    e_stmvsprw      0x14 (r1)           ;# Save CR, LR, CTR, XER
    se_mtLR     r3                      ;# Copy ISR address (from IACKR) to LR for next branch
    e_stmvgprw      0x24 (r1)           ;# Save GPRs, r[0,3-12]
    se_blrl                             ;# Branch to ISR, with return to next instruction (epilogue)

epilogue:
    e_lmvsprw       0x14 (r1)           ;# Restore CR, LR, CTR, XER
    e_lmvgprw       0x24 (r1)           ;# Restore GPRs, r[0,3-12]
    e_lis       r3, INTC_EOIR@ha        ;# Load upper half of INTC_EOIR address to r3
    mbar                                ;# Ensure prior clearing of interrupt flag conmpleted.
    wrteei      0                       ;# Disable interrupts
    e_stw       r3, INTC_EOIR@l(r3)     ;# Load lower half of INTC_EOIR address to r3 and
                                        ;# write contents of r3 to INTC_EOIR
    se_lwz      r3, 0x08 (r1)           ;# Restore working register (r3) (original value)
    e_lmvsrrw       0x0c (r1)           ;# Restore SRR[0-1]
    e_add16i    r1, r1, 0x50            ;# Reclaim stack space
    se_rfi                              ;# End of Interrupt Handler - re-enables interrupts

Hope it helps.

Stan

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Contributor III

Thank you Stan.

Regarding your comment "You will need to add the instruction to save/restore  SRR registers", I think it is already there:

e_stmvsrrw      0x0c (r1)
...
e_lmvsrrw       0x0c (r1)           ;# Restore SRR[0-1]

Thank you,

David

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8 Views
NXP Employee
NXP Employee

Hi David,

Thanks for your comment!

You are absolutely right. SRR0/SRR1 store/restore is already included in the snippet above.

Stan

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