S32 Design Studio - S-Record with Boot Header (MPC5746C)

[cholland]

Hi,

I noticed in one of my projects, the SREC has the boot record embedded in the record, the second project does not.

   S30900FA0000005A0002A0   /* Boot Header */
   S30900FA001001000000EB   /* Program Code Start Address */

I believe all I have to do is, in the project properties, under C/C++ Build Settings, in the Standard S32DS C Compiler Section, I double click the START_FROM_FLASH symbol. So, I did that.

When I recompile, I still do not see the Boot header. "005A0002"

One more thing I would like to add is that the S-Record format for the 2 projects is different.

In the first project, the S-Record format is S0, S3 15, S7, (which is ideal)

In the second project, the S-Record format is S0, S2 14, S8. (which is not ideal. the length is only 15 bytes)

I'm not sure if it's because the program code location is different? I don't think that should matter.

I use the exact same setting as the first project

Incidentally, I would also like to know what the check boxes are for the sections -j .text are for as well, if anybody happens to know?

Thank you,

This is where I am trying to locate the Boot Header and Program Code

MEMORY
{

flash_rchw : org = 0x00FC0000, len = 0x4    /* This is the Boot Header address location */
cpu0_reset_vec : org = 0x00FC0000+0x10, len = 0x4 /* This is the Program Address Offset */
cpu2_reset_vec : org = 0x00FC0000+0x04, len = 0x4

m_text : org = 0x00FC8000, len = 224K
m_data : org = 0x40000000, len = 192K
}

[cholland]

Hi Jiri,

Thanks for the reply, but your startup.s is different from mine. My Startup.S is just assembly code.

The closest thing is the 57xx_flash.ld file. In there it describles the rchw location.

I am not sure if it necessarily means it will put a boot header at that location and what the contents will be?

I'm not sure where the contents of the boot header is?

MEMORY
{

flash_rchw : org = 0x00FC0000, len = 0x4
cpu0_reset_vec : org = 0x00FC0000+0x10, len = 0x4
cpu2_reset_vec : org = 0x00FC0000+0x04, len = 0x4

m_text : org = 0x00FC8000, len = 224K
m_data : org = 0x40000000, len = 192K
}

SECTIONS
{
.rchw :
{
KEEP(*(.rchw))
} > flash_rchw

Thanks anyway,

[jiri_kral]

Hi, 

the BootHeader must be present in the code - ideally in startup.S. Mine startup (default one) is also assembly file, but you can see that there is store RCHW_VAL to .rchw section on address (taken from linker file) 0xFA0000. So, it is user responsibility add bootheader to one of the 11 addresses. You can find more details in chapter 55.1.4 (page 2250 in reference manual https://www.nxp.com/docs/en/reference-manual/MPC5746CRM.pdf  )

The different situation is for RAM target, there is no rchw section present and boot is done by debugger. 

Jiri 

[cholland]

Hey Jiri,

I was missing the file called "flashrchw.c". That's what was causing the missing boot header in the .srec file.

I also noticed that when I moved the program code to 0x0010000, the srec format changed, so the srec format is dependent

on where the program code is located. (Kind of odd)

I have an assortment of srec tools { srec_cat.exe, srec_cmp.exe, srec_info.exe, SRecCvt.exe, SRecConv_v2.exe }

I don't know how I even got the file in the first place?

Thanks for your help,

Content of the flashrchw.c file

#if defined(START_FROM_FLASH)
#include "typedefs.h"

#define MPC57xx_ID 0x005A0000 /* RCHW boot ID for MPC57xx devices */
#define VLE_ENABLE 0x01000000 /* VLE is enabled */

#define CPU2_ENABLED 0x00000001
#define CPU0_ENABLED 0x00000002
#define CPUC_ENABLED 0x00000004
#define CPU1_ENABLED 0x00000008

#if defined(MPC574xP) || defined(MPC5777C) || defined(MPC577xK)
extern void _start(void);
#define ENTRY_POINT _start
#define RCHW_VAL (VLE_ENABLE | MPC57xx_ID)
#else
#if defined(TURN_ON_CPU0) && defined(TURN_ON_CPU1) && defined(TURN_ON_CPU2)
#define TARGET_CORES (CPU0_ENABLED | CPU1_ENABLED | CPU2_ENABLED)
#elif defined(TURN_ON_CPU0) && defined(TURN_ON_CPU1)
#define TARGET_CORES (CPU0_ENABLED | CPU1_ENABLED)
#elif defined(TURN_ON_CPU0) && defined(TURN_ON_CPU2)
#define TARGET_CORES (CPU0_ENABLED | CPU2_ENABLED)
#elif defined(TURN_ON_CPU1) && defined(TURN_ON_CPU2)
#define TARGET_CORES (CPU1_ENABLED | CPU2_ENABLED)
#elif defined(TURN_ON_CPU0)
#define TARGET_CORES (CPU0_ENABLED)
#elif defined(TURN_ON_CPU1)
#define TARGET_CORES (CPU1_ENABLED)
#elif defined(TURN_ON_CPU2)
#define TARGET_CORES (CPU2_ENABLED)
#else
#error "Neither core is selected"
#endif /* defined(CPU0) && defined(CPU1) && defined(CPU2) */
#define RCHW_VAL (MPC57xx_ID | TARGET_CORES)
#endif

const uint32_t __attribute__ ((section(".rchw"))) RCHW1 = RCHW_VAL;
#if defined(MPC574xP) || defined(MPC5777C) || defined(MPC577xK)
const uint32_t __attribute__ ((section(".cpu0_reset_vector"))) RCHW2 = (uint32_t)ENTRY_POINT;
#else
#if defined(TURN_ON_CPU0)
const uint32_t __attribute__ ((section(".cpu0_reset_vector"))) RCHW2_0 = (uint32_t)0x1000000;
#endif
#if defined(TURN_ON_CPU1)
const uint32_t __attribute__ ((section(".cpu1_reset_vector"))) RCHW2_1 = (uint32_t)$(FLASH_START_2);
#endif
#if defined(TURN_ON_CPU2)
const uint32_t __attribute__ ((section(".cpu2_reset_vector"))) RCHW2_2 = (uint32_t)$(FLASH_START_3);
#endif
#endif
#endif /* defined(START_FROM_FLASH) */

[jiri_kral]

Hi, 

please check startup_MPC5746.S file - that's where RCHW_VAL is normally defined for S32DS Projects and added into .rchw section: 

For different s-record formats you can use for example srec_cat tool: 

srec_examples 

Another good article related to srec formating is here: 

CRC Checksum Generation with ‘SRecord’ Tools for GNU and Eclipse | MCU on Eclipse 

Jiri