MPC5746R.h etpu errors in S32DS v1.2

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MPC5746R.h etpu errors in S32DS v1.2

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jamesmurray
Contributor V

I've found what I believe to be some errors in the MPC5746R.h file that is generated by S32DS for Power Architecture v1.2

Some of the eTPU registers have the wrong addresses. I spent 2-3 hours single-stepping code as it kept hitting the IVOR1 exception.

Steps to recreate:

-create a new S32DS project for MPC5746R

-examine include/MPC5746R.h

This is wrong:

struct eTPU_CCCR_tag {
  uint8_t eTPU_CCCR_reserved0[1024];  <--- wrong!
  eTPU_CCCR_ENG1_C_tag ENG1_C[32];
  uint8_t eTPU_CCCR_reserved1[512];
  eTPU_CCCR_ENG2_C_tag ENG2_C[32];
};

Because..

#define eTPU_CCCR_0 (*(volatile struct eTPU_CCCR_tag *) 0xFFCC0400UL)

From the V1.6 version of MPC5746RRM page 89.

0x400 eTPU_CCCR_C0CR_ENG1 - eTPU 1 Channel 0 Configuration Register

i.e. the header file is adding the 0x400 offset twice.

Same kind of problem here:

struct eTPU_TBR_tag {
  uint8_t eTPU_TBR_reserved0[32]; <--- wrong!
  eTPU_TBR_TBCR_ENG1_tag TBCR_ENG1;    /* eTPU Engine 1 Time Base Configuration Register */
  eTPU_TBR_TB1R_ENG1_tag TB1R_ENG1;    /* eTPU Engine 1 Time Base 1 (TCR1) Visibility Register */
  eTPU_TBR_TB2R_ENG1_tag TB2R_ENG1;    /* eTPU Engine 1 Time Base 2 (TCR2) Visibility Register */
  eTPU_TBR_STAC_ENG1_tag STAC_ENG1;    /* eTPU Engine 1 STAC Configuration Register */
  uint8_t eTPU_TBR_reserved1[16];
  eTPU_TBR_TBCR_ENG2_tag TBCR_ENG2;    /* eTPU Engine 2 Time Base Configuration Register */
  eTPU_TBR_TB1R_ENG2_tag TB1R_ENG2;    /* eTPU Engine 2 Time Base 1 (TCR1) Visibility Register */
  eTPU_TBR_TB2R_ENG2_tag TB2R_ENG2;    /* eTPU Engine 2 Time Base 2 (TCR2) Visibility Register */
  eTPU_TBR_STAC_ENG2_tag STAC_ENG2;    /* eTPU Engine 2 STAC Configuration Register */
};

Because:

#define eTPU_TBR_0 (*(volatile struct eTPU_TBR_tag *) 0xFFCC0020UL)

Page 86:

0x20 eTPU_TBR_TBCR_ENG1 - eTPU 1 Time Base Configuration Register

i.e. the header file is adding the 0x20 offset twice.

These are the only two I found, I do not know if that kind of error is repeated elsewhere. A thorough review would be advised.

Should I create a support ticket for this or is it sufficient to post here?

regards

James

12 Replies

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jyothsnarajan
Contributor V

Hi,

I running  into the same problem (IVOR1- thread suspended) error . The MPC5746R.h header file has not yet  been changed to  address the issue reported above. 

NXP please send me the latest and corrected version of the header file for MPC5746R.h.  Please also post here the changes that I need to make to get over the IVOR1 error., 

Thank you

jsmcortina

@Denis Fedorov

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261 Views
denisfedorov
NXP Employee
NXP Employee

Hello Jyothsna,

Unfortunately we do not have corrected version of header file.

Currently we have header v.5.0.3 in DS.

I do not know when we get new corrected version.

Denis Fedorov

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jamesmurray
Contributor V

There are also errors with CAN ID_EXT field, LINFLEX IFCR (not present on most modules).

The EMIOS definition is totally broken. I found the mpc563m.h way of defining EMIOS was more useable.

I've reported all of these, but checked for an update and am not seeing one.

James

261 Views
jyothsnarajan
Contributor V

James,

Thank you for confirming that the errors still exist. 

I tried Denis's suggestion of making all base address the same and allowing the offsets within the structs but I still get the IVOR1 error. 

This problem is slowing down my work.  I want to get past the header file issues so I can work on my code.  Can you please try to build a simple but functional eTPU application for MPC5746 with S32DS and post here?  I used AN2849 instructions and associated software.

Can you share the changes required to fix only the eTPU part of the header file for now?

Can you give me the JIRA number for this issue?

JoyR

jsmcortina

@Denis Fedorov

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jamesmurray
Contributor V

Here are the sections I changed:

------------------

struct eTPU_CCCR_tag {
/*  uint8_t eTPU_CCCR_reserved0[1024]; JSM - This is incorrect according to reference manual rev 6.1 */
  eTPU_CCCR_ENG1_C_tag ENG1_C[32];

etc.

------------------

struct eTPU_ER_tag {
/* uint8_t eTPU_ER_reserved0[96]; JSM - This is incorrect according to reference manual rev 6.1 */
  eTPU_ER_WDTR_ENG1_tag WDTR_ENG1;     /* eTPU Watchdog Timer Register for Engine 1 */
etc.

------------------

struct eTPU_GCR_tag {
/*  uint8_t eTPU_GCR_reserved0[512];  JSM - This is incorrect according to reference manual rev 6.1 */
  eTPU_GCR_CISR_ENG1_tag CISR_ENG1;    /* eTPU Channel Interrupt Status Register for Engine 1 */

etc.

------------------

struct eTPU_TBR_tag {
/*   uint8_t eTPU_TBR_reserved0[32]; JSM - This is incorrect according to reference manual rev 6.1 addendum page 86 */
  eTPU_TBR_TBCR_ENG1_tag TBCR_ENG1;    /* eTPU Engine 1 Time Base Configuration Register */

etc.

With these changes I have been using the eTPU with my own code.

Hope that helps.

James

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jyothsnarajan
Contributor V

Hi James,

I tried your suggestion and am still getting the IVOR1.  I am trying to integrate the etpu pwm application with the mpc code. I followed directions in AN2849 and used the pwm source files to create my own project for MPC5745.

I get the IVOR1 when I step into the fs_etpu_init() function. All it does it copy the eTPU opcodes and globals into memory. 

Is it possible to post a very bare minimum S32DS project that integrates the eTPU pwm function set with the MPC5746 code? 

This is my first try at integrating the eTPU code  and with the IVOR1 am not able to establish if the problem is with the code that integrates the eTPU code with host ( the fs_etpu_xxx functions) or with the eTPU code itself. 

I use MPC5745R and my understanding is that other than the flash/sram size, all else is same between MPC5746/5745R, including  eTPU  coniiguration register addresses .  When creating the S32DS Project , I select MPC5745 which selects the right linker file for the processor. Please confirm that this is the case.

Appreciate your help.

Best,

JoyR

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jamesmurray
Contributor V

I'm not using any NXP/Freescale code, so I'm afraid I can't help there, I wrote my own.

All I can suggest is to use the assembly-step mode and find out exactly what opcode and registers are triggering the IVOR1.

James

261 Views
denisfedorov
NXP Employee
NXP Employee

Hello James,

I think this defines are wrong:

#define eTPU_CCCR_0 (*(volatile struct eTPU_CCCR_tag *) 0xFFCC0400UL)
#define eTPU_ER_0 (*(volatile struct eTPU_ER_tag *) 0xFFCC0060UL)
#define eTPU_GCR_0 (*(volatile struct eTPU_GCR_tag *) 0xFFCC0200UL)
#define eTPU_LMR_0 (*(volatile struct eTPU_LMR_tag *) 0xFFCC0080UL)
#define eTPU_MESR_0 (*(volatile struct eTPU_MESR_tag *) 0xFFCC0100UL)
#define eTPU_SCR_0 (*(volatile struct eTPU_SCR_tag *) 0xFFCC0000UL)
#define eTPU_SSIR_0 (*(volatile struct eTPU_SSIR_tag *) 0xFFCC0C00UL)
#define eTPU_TBR_0 (*(volatile struct eTPU_TBR_tag *) 0xFFCC0020UL)

They should point to the same base address of eTPU 0xFFCC0000UL

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jamesmurray
Contributor V

That's one way to fix it, but it seems incorrect, then you have multiple 'reserved' arrays that overlap real register addresses.

James

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denisfedorov
NXP Employee
NXP Employee

James, look at other header files in MPC57xx they all built with overlapped reserved arrays. There is nothing wrong with this approach.

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jamesmurray
Contributor V

I found another one:

struct eTPU_GCR_tag {
/*  uint8_t eTPU_GCR_reserved0[512];  <--- nope */
  eTPU_GCR_CISR_ENG1_tag CISR_ENG1;    /* eTPU Channel Interrupt Status Register for Engine 1 */
  eTPU_GCR_CISR_ENG2_tag CISR_ENG2;    /* eTPU Channel Interrupt Status Register for Engine 2 */

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jiri_kral
NXP Employee
NXP Employee

Hello James, 

thanks for report. I can confirm that the address ranges are wrong - as you discovered. I'll rise JIRA ticket for apps team with your data. 

Jiri  

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