Every time s32k3 runs to Mcu_DistributePllClock, the following error is reported.

[ct5ctl]

I just started to contact s32k series products.

Every time s32k3 runs to Mcu_DistributePllClock, the following error is reported. What is the problem?

[danielmartynek]

Hello @ct5ctl,

Which S32K3 part do you have?

Do you use a certain RTD example or is it your custome code?

If it is your code, please share it so that we can test it on our side.

Is the HSE_FW enabled on the chip?

Regards,

Daniel

[ct5ctl]

And when I use a non-mcal example, the following error will be reported when I run to Clock_Ip_Init(&Clock_Ip_aClockConfig[0]);, which is also related to pll. Is pll not set?

[danielmartynek]

Hello @ct5ctl,

If you did not program the HSE_FW, it is not enabled, and we can exclude that.

Do you use an EVB or your own board?

Which RTD version do you use?

Can you update the letest one?

Thanks,

Daniel

[ct5ctl]

The development board I use is S32K344_257BGA, as shown in the figure below

The RTD version I am using now is 2.0.1, I try to download and install the latest version of RTD (in the red frame), including mcal and sdk. But my s32ds can't recognize the latest version of RTD, what's the reason?

[danielmartynek]

Can you try updating to 2.0.2 only.

Thank you.

[ct5ctl]

Is there something wrong with my clock setting?

[danielmartynek]

Hello @ct5ctl,

Thanks for providing the EVB version and the clock configuration.

The board has 40MHz crystal according the schematic of the S32K3-T-Box.

Can you change it in the configuration tool?

Thank you,

BR, Daniel

[ct5ctl]

The chip package I had previously selected was 256 and now switched to the correct chip package 172.

The current situation is: every time I debug to Mcu_DistributePllClock(), it will get stuck, as shown in the figure below

[ct5ctl]

And The main control chip package of my EVB is s32k344MaxQFP-172, As shown below

[ct5ctl]

Forgive me, can you tell me how to switch to 40MHz crystal in the configuration tool? Or give me some tutorials related to clock setting
Thank you

[danielmartynek · Accepted solution]

Hello @ct5ctl,

This is all you need to change in the configuration tool and update the generated code:

• FXOSC  to 40MHz
• PLL to (/2 * 48)

[ct5ctl]

hi, I tried to update to the 2.0.2 version of the RTD (Include mcal and sdk) and use a CAN example of the RTD, but it still reports an error at Mcu_DistributePllClock()

[ct5ctl]

Hi Daniel, thank for your reply.
But I still get an error when I use the RTD example
My debuger is Multilink.
And how to enable the HSE_FW ？