About the setting of PLL1

[578294688]

Hello,I have a new problem about the setting of PLL1,please see the pictures:

this is a setting I tried,but I am failed,in this setting,I set the " PLLDIG_PLL1FD[FDEN] = 0b " In the reference manual,the PLL1 VCO should be 48MHz * 20 = 960MHz

isn't it?

[jiri_kral]

Hi, 

what is your MCU - assume some PPC - but which particular one? 

Jiri

[578294688]

I'm sorry,Jiri.I don't quite understand what your means.

My MCU is S32R274,for this question,the result is inconsistent with my assumptions.

In addition,I want to ask you for another problem,what does the VCO mean?

Thank for your help.

[jiri_kral]

Hi, 

it looks like that you don't have enabled Fractional divider in PLL1 settings: 

The VCO means Voltage-controlled oscillator. More info about Fractional Divider you can find in Reference Manual chapter 34.4.3.1 (page 1226 - S32R274 Reference Manual, Rev. 4, 05/2018 ). 

Hope it helps. 

Jiri 

[578294688]

Hello,Jiri.

I get your means,but I want to know why I disable the Fractional divider,the result is inconsistent with my assumptions.

For example,I set the parameters same as the question.I think the VCO should be 960MHz,but the result is 48MHz,I don't know why?The equation is that:

To my understanding,the Fpll1_ref is 48MHz,MFD is 20,the pll1_VCO should be 960MHz.

Thank for your help today.

[jiri_kral]

Hi, 

I went through RM - and you are right. When the FD is disabled - the output should be in your case 960MHz. So - I'll report this as a Processor Expert bug. Thank you for report. In my opinion - the real HW will work as expected. But I didn't test it yet. 

Jiri

[578294688]

Hello,Jiri.

Thank for your response,actually,I don't test on the board.I think this is the bug of the IDE,I will test it on the board in the last two days.

Thank for your help.