Hi 明超 戴,
Please check capacitor at RESET pin.
The Too big time constant of RC circuit at RESET pin could interfere with COP/CM reset source detection ability.
In short: In the case of a reset, RESET pin will be hold down for 128 OSCCLK cycles. The voltage level at RESET pin will be detected after next 64 OSCCLK cycles. When the low-level voltage is detected, the External Reset source is assumed and POR reset vector is selected.
So, we have to ensure that voltage at RESET pin will achieve high voltage level prior these 64 OSCCLK cycles.
For example, if we take the case when we use 16MHz oscillator, 64 SYSCLK cycles presents 4us.
Therefore, if we have 2.2kOhm pull-up resistor at RESET pin, the capacitance at RESET pin should be below approximately 1.8nF. Otherwise, we detect POR / LVR / Illegal Address Reset / External Reset.
Note: Simply RC cell, RC constant=Tau=R*C represents the time when voltage achieves approximately 2/3 value. Detection level for high value at the pin is also approximately 2/3 value of VCC. So we can use simple calculation: C<64/(R*fOSC). In the calculation, we omitted capacitance and internal pull-up of RESET pin.
For more details please check:
https://community.freescale.com/docs/DOC-103737
Note: There is one additional option. We could connect Schottky diode between MCU reset pin and external RC circuit (capacitor and pull-up). In the case of system reset (caused by MCU), the external capacitor isn’t discharged and COP/CM detection works correctly even with 100nF capacitor. See attached circuit:

I hope it helps you.
Have a great day,
RadekS
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