Hi,
It can wake-up either by the real-time interrupt, or by a falling edge on PP2.
The signal on PP2 is also connected to ECT pin IOC3/PT3. The idea is that the falling edge on PP2 wakes the processor up, and that the ECT interrupt is then called to record the time.
The pulses can be 160us in length, and 2ms apart. The first few pulses sent are not always picked up by the processor, as if it were taking a while to wake-up from pseudo-stop. The delay varies, but is sometimes 4 or more pulses - a time of over 6ms!
Once the processor is awake, or if it is in Wait mode, no pulses are missed. This is not using the PLL.
Oscillator start-up time tUPOSC can vary from 8 to 100 ms.
Maximum value is for extreme cases using high Q, low frequency crystals.
tUPOSC is that only applies when the processor is coming out of Stop mode. For Pseudo-stop, is it not the case that the processor should wake up after tWRS = 14 bus cycles = 560ns.
The recovery from Pseudo STOP and Wait are the same. It should be tWRS = 14 bus cycles.
5 to 10 us Wake-up pulses is too short. They should be larger than 10 us. It is probably the reason why the microcontroller may miss some of them. Refer to Table A-6 5V I/O Characteristics in the reference manual package:
9S12DP512_ZIP
MC9S12DP512 Data Sheet and Reference Manual, zip format. Covers also the MC9S12DT512, MC9S12DJ512, and MC9S12A512
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=S12D&fpsp=1&tab=Documentation_Tab
