value mask filter How to set "Receive cycle counter filter value" and "Receive cycle counter filter mask" ? I had seen "CYCCNT^MBCCFRn[CCFMSK] = MB

[leidou]

Hello,

Thank you for your reply. This is my first time asking question in NXP Community. I chose the wrong options. It is not a i.MX Processors problem. It is about MC9S12XF512. I had seen the answers for "How to Calculate Cycle Counter Value/Mask ", but no one gave the answers. Someone even said " It's a freescale mystery...". I will be very grateful if you can help me.

Have a great day,

Lei

[dianabatrlova]

Hi Lei,

I added here the received example from the application engineer.

Example: The application wants to receive a frame in every 4th cycle, start in cycle 1.

1. The periodicity is configurable by the CCFMSK – cycle counter filtering mask

                CCFMSK = Perioda-1 = 4-1=3

1. The start offset is done by configuring the CCFVAL – cycle counter filtering mask

                CCFVAL = in which cycle to start = 1

1. We need to enable the cycle filtering by set the CCFE bit

Best regards,

Diana