Hello, Devkit-S12XE includes a bug on the PORT J2. This document shows the correct connection. The pin designation in the schematic, QSG, and pin markings on the board does not correspond to the connection on the board. Schematic: https://www.nxp.com/downloads/en/schematics/DEVKIT-S12XE-SCH.pdf  QSG: https://www.nxp.com/docs/en/quick-reference-guide/DEVKIT-S12XE-QSG.pdf  Pin markings on the board: In particular, these are the following pin numbers of PORT J2 where the bug was found: 16, 17, 18, 19 The real connection is as follows: I hope it helps, Best regards, Diana

Attached zip file contains three Code Warrior project for MagniV devices (S12ZVM, S12ZVL and S12ZVC). Each of them demonstrates usage of High Voltage Input feature. Find detailed description in the header of main.c file of the CW project.

The S12Z devices contain unmaskable machine exception interrupt for severe system problems. The Memory Map Control module (MMC) generates this exception in the case of illegal memory access and uncorrectable ECC errors. The MMCECn register is set to a non-zero value if an S12ZCPU access violation or an uncorrectable ECC error has occurred. At the same time when this register is set to a non-zero value, access information is captured in the MMCPCn (program counter) and MMCCCRn (CCR U, X and I bits) registers. The MMCECn registers are cleared by writing the value 0xFFFF. Unfortunately, the exact address with corrupted data isn’t stored in any user-accessible register and this makes the debugging more difficult.   In the case of reading memory with an uncorrectable ECC error, the MMC causes jump to the address in the Machine Exception vector as soon as the current instruction finishes execution. This may be used in workaround code for detection of the exact address with corrupted data. See attached example code. Note: The code detects only the first address of the phrase with uncorrectable corrupted data. The solution for detecting multiple ECC issues isn't included.     The execution of a machine exception code isn’t straightforward in this case. Please read the simplified procedure: The reading of uncorrectable corrupted data (double bit ECC error) will invoke machine exception. The ma_counter variable is incremented to 1. The MMCEC register is checked for detection of machine exception source. If ECC at EEPROM or P-Flash is detected as a machine exception source, the sequential reading of appropriate memory starts. Note: Since the P-FLASH is protected by 39-Bit ECC Scheme, we should read at leats single word(byte) from every aligned 32bit phrases. The global variable add contains a current reading address. When CPU read the uncorrectable corrupted data again, the MMC causes jump to the address in the Machine Exception vector again. The ma_counter variable is incremented to 2. When ma_counter is 2, we may store add variable address with corrupted data, clear ma_counter and clear pending flags in MMCEC register. Application project-specific user code for machine exception case may be applied (signalization, repair,…) Please be aware that no information is stored on the stack during entering machine exception handler (missing return address). So, default RTI instruction on end of routine cannot be used for returning to the application code. We must end the machine exception routine by MCU reset or jump to some known code entry point or by an endless loop.  This code is only a simple example code and does not cover all conditions. More details regarding simulating ECC issue at EEPROM and P-Flash: S12Z - Simulating ECC errors at EEPROM by cumulative write  https://community.nxp.com/docs/DOC-334327 

This presentation walks you through the features and specs of the most integrated solution for CAN node applications. Details @ http://www.freescale.com/S12magniV

In the ZIP file you can find two CodeWarrior projects, one for S12ZVM and other for S12ZVL device, demonstrating the trimming of Autonomous Clock (ACLK - trimmable internal RC-Oscillator) which can be selected as clock source for some CPMU features. Also the Autonomous Periodical Interrupt feature using the trimmed ACLK as a clock source is demonstrated too in this SW example.