I would like to apologize for our delay.
You are right, there is issue in AN3144SW. I will report this issue to our documentation team.
About 1)
No, in this case – difference between XDT and XDP is just in size of RAM, number of CANs and one IIC module – nothing important.
About 2)
Since Buffer0 is used by both cores, it must be placed in RAM area which is visible by both cores. Please add placement definition for Buffer0 definition – For example:
@main.c
#pragma DATA_SEG SHARED_DATA
extern tBuffer Buffer0;
#pragma DATA_SEG DEFAULT
@xgate.cxgate
#pragma DATA_SEG SHARED_DATA
tBuffer Buffer0;
#pragma DATA_SEG DEFAULT
SCI baud rate setting is adjusted for 25MHz bus clock however example code doesn’t contain PLL initialization. Please update SCI baud rate settings according your bus clock and requested speed.
For example: I used 16MHz crystal therefore bus clock = 8MHz. SCI0BD = bus clock/16/baud rate=8000000/16/19200=26
AN3144SW initialize also terminal window however this terminal has to be set according your demands, or you can close Terminal window and use any other terminal like Hyper terminal inside WinXp.
Please go to menu-Terminal-Configure connections-Select Defaul Configuration (for example Serial port)-Set appropriate serial port and BaudRate.
About3)
Unfortunately simulation of interrupts isn’t very convenient. If it is possible I would like to recommend testing code on real device.
Note: In attachment you can find another simple example code for “SCI gateway”.
I hope it helps you.