mm9z1-638: current ampere hour wakeup question

[gumu]

Dear Sir,

When debugging the Ampere timing wake-up feature, I encountered an issue. The actual testing scenario here is constant discharge at 10mA with 100 sampling points per second. The wake-up threshold is set to 10000. However, the actual result is that the device takes approximately 20 seconds to wake up, which is exactly double the expected value. I have checked the PCR_CTL.PF registers, and their values are all 0. I would like to know what other configurations need to be checked.

code:

static void CurrentWakeupCfg(u32 current_ah_thres)
{
	if (!current_ah_thres)
	{
		current_ah_thres = 100;
	}

	B_ACQ_TCMP = ADC_CURRENT_SAMPLE_PERIOD; //10						//measure every 10ms in sleep  LP clock = 1KHz, depends on PF[1:0] setting
	
	B_ACQ_CTH = (CURRENT_THRESHOLD_WAKEUP >> 1);        			// config to wakeup if |I| > 500mA
	B_ACQ_THF = 0;      											//filtering

	// config to wakeup if Ah counter >xxx
	B_ACQ_CTL = B_ACQ_CTL_AHCRM_MASK | B_ACQ_CTL_AHCR_MASK; 		// reset Ah counter
	B_ACQ_AHTH = current_ah_thres; 									// 10mA * 10s * 100S/s

	ADCLpEnable(); 

	B_PCR_WUEH_WUAHTH = 1;  //Wake-up on Ah counter enabled
	B_PCR_WUEH_WUCTH = 1;   //Wake-up on current threshold Flag
}

Please see the waveform:

Thanks!

[Q_man]

Hi Mu,

seems that taking the measurement takes longer than 10ms, which will result in a sample taken every 20ms.

The Sigma Delta ADC requires some time "Latency" till a valid result is available after the decimation / filtering. This Latency depends on the decimation DF (ODR output data rate) and other settings:

You can also check the VDDA supply to see when the ADC is active (VDDA=2.5V) in low power mode, e.g.:

Hope this helps!

W.

[gumu]

Hi @Q_man ，

Thanks！

I just measured waveform of VDDA in stop mode. 

Is it normal for VDDA to frequently fluctuate between high and low levels?

[Q_man · Accepted solution]

Hi Mu,

the picture matches my expectations and the observed "issue"!

Taking one measurement takes ~10ms (latency explained above).

Setting the period to also 10ms conflicts and results in 20ms period.

Most likely it makes sense to change the desired period to a bigger value (e.g. every 100ms or 1000ms), which will then work as expected and will reduce the average current consumption.

W.

[gumu]

Hi @Q_man ,

Thank you!

Considering the latency time of the ADC sampling, the maximum sampling frequency in stop mode is 50Hz. Now, after changing it to 25Hz, the results were mostly normal. Below is the waveform for the VDDA with a sampling period of 25Hz in stop mode.