Hi,
The pin 38
38 PS5 / KWS5 / MOSI1 / TXD1 / IOC0_2
37 PS4 / KWS4 / MISO1 / RXD1 / IOC0_3
The pin description in the table 1-6 presents>
38 PS5 KWS5 MOSI1 TXD1 IOC0_22
The default function is GPIO in input mode. All other function have priority from left(lowest) to right(highest).
If the alternative peripheral/peripherals is/are enabled at the pin then the peripheral with the highest priority takes precedence over other and controls the pin. So if the pin is used as SCI then there is nothing necessary to be set and the pin works like Rx/Tx pinr SCI.
Moreover it is worth to look on the default connection of the peripheral to the pin. In this case, for SCI1, the Rx/Tx can be routed by MODRR register to
Bit 5 of MODRR0, SCI1RR, Module Routing Register — SCI1 routing
(Table 2-4. MODRR0 Routing Register Field Descriptions)
1 TXD1 on PT1; RXD1 on PT0
0 TXD1 on PS5; RXD1 on PS4
The default status of the bit is 0 so TXD1 is on PS5 by default.
BTW, The bootloader selection pin is selected in the config,h file…
Best regards,
Ladislav