clock settings for MC9S12ZVMC128

[maharajsankaran]

Hi all,

we are using the MC9S12ZVMC128 from S12Z family.we try to set the clock to 100MHz.

but we are facing problem like not able to debug.Please share if any procedure need to follow.

Here We attached the code for your refenence.

Regards,

Raja S

Original Attachment has been moved to: freescale_share.c.zip

[RadekS]

Hi maharaj,

I shortly looked at your code:

1. I do not understood your command CPMUIFLG = 0x00;.  Writing or writing 0 has no effect on CPMUIFLG register bits.
2. COP is disabled after reset when your FPROT values in Flash are default (0xFF). Execution of CPMUCOP_REG = CPMUCOP_DISABLE_MASK; command will cause, that COP watchdog cannot be enabled until next reset – you cannot use it for software reset. I suppose that you don’t use COP for MCU reset. Correct?
3. Your command CPMUCLKS = CPMUCLKS | COPOSCSEL0_MASK; do not make sense since it is placed below CPMUCOP_REG = CPMUCOP_DISABLE_MASK command. COPOSCSEL0 bit could be configured in normal mode only prior you enable/disable COP watchdog.
4. CPMUIFLG_REG_ADDR and CPMUIFLG are defined twice.
5. I suppose that CRGFLG is CPMURFLG register, but I do not understood why you write 0x00
6. Your clock settings for 50MHz bus clock looks OK
7. Command CPMUPLL = 0u; should be prior you start configure SYNR, REFDV, POSDIV registers. Write to CPMUPLL register clears the LOCK and UPOSC status bits.

As AMEY already mentioned we know about some BDM connection issues during stepping over PLL init code. The second link in AMEY’s post contains workaround.

Which BDM debugger you use? If I remember correctly there were some issues with USB Multilink Rev.C (USB-ML-12E) with very old firmware.

I hope it helps you.

Have a great day,
RadekS

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[ameykhatavkar]

Hi Raja,

Please look at answer here:Re: what is the difference between S12X and S12z MagnaV core?

S12ZVMx12EVB PLL configuration with External crystal.

There are sometimes problems caused by running the debugging interface with bus-clock speeds close to the limit the Multilink cables can actually support on the BDM interface (the limit is 50MHz, IIRC).

To resolve this the BDC interface can be set to use the fixed IRC clock (1MHz) instead of the bus-clock, so that the communication with Multilink is not affected by changes in the clocking set-up.

This is how to do it in CW 10.6:

1. Go to "Run/Debug settings" in your project's "Properties".
2. Select the Multilink connection from the list presented and click on "Edit".
3. In the "Main" Tab, "Target settings" click on the "Edit..." button next to the "Connection:" field.
4. Uncheck the option "Use Bus Clock as Debug Controller (SIBDC) Clock Source {Default = Checked}" under "Connection" -> "Additional Options".
5. Click on "Ok" in each of the three open windows.

Regards,

Amey