Xgate on HCS12XEP100 demo board problems

Claudione · ‎06-04-2013

Hello guys.

I'm going to use the xgate feature on HCS12XEP100 demo board. I use HCS12 core since 2000 and I solved my problem step by step.

but I don't understand where is my mistake or defects about xgate core now.

I saw a lot of examples, just to start and trigg an event for xgate but I don't have results for a week at least.

My os works properly in the HCS12 core. I tested it by and I didn't have any problem to use the HCS12XEP100 demo board.

I use it, managed from PE micro USB multilink (rev.C).(I think it's correct to use bdm & demoboard)

But XGATE doesn't want to work.

I started with a project from wizard, afterwards I moved the xgate vector table in the non banked section flash (Rom C000). It seems to be reasonable.

But I don't trigg any interrupt.

I post my code for help.

Thanks a lot.

Claudio.

#pragma push

/* Two stacks in XGATE core3 */

#pragma DATA_SEG XGATE_STK_L

word XGATE_STACK_L[1];

#pragma DATA_SEG XGATE_STK_H

word XGATE_STACK_H[1];

#pragma pop

/************************************************************************************************************************************************************/

/* Defines the macro to switch the interrupt selected to the Xgate coprocessor */

/************************************************************************************************************************************************************/

#define ROUTE_INTERRUPT(vec_adr, cfdata) \

INT_CFADDR = (vec_adr) & 0xF0; \

INT_CFDATA_ARR[((vec_adr) & 0x0F) >> 1] = (cfdata)

/************************************************************************************************************************************************************/

/* Enable Xgate coprocessor */

/************************************************************************************************************************************************************/

static void SetupXGATE(void)

{

XGMCTL = 0;

while(XGCHID);

XGVBR = (unsigned int)(void*__far)(XGATE_VectorTable - 0x09); // XGATE vectors offset

ROUTE_INTERRUPT(0x72, 0x81); // software trigger 0

XGISPSEL= 1;

XGISP31= (unsigned int)(void*__far)(XGATE_STACK_L + 1);

XGISPSEL= 2;

XGISP74= (unsigned int)(void*__far)(XGATE_STACK_H + 1);

XGISPSEL= 0;

XGMCTL= 0xFBC1;

XGSWT = 0x0101; // enable software trigger 0

}

/************************************************************************************************************************************************************/

/* C main program */

/************************************************************************************************************************************************************/

void main(void)

{

SetupXGATE();

EnableInterrupts;

for(;;)

{

_FEED_COP();

}

/************************************************************************************************************************************************************/

/* XGATE vectors table. */

/************************************************************************************************************************************************************/

#pragma CONST_SEG XGATE_VECTORS // xgate vectors segment

const XGATE_TableEntry XGATE_VectorTable[] =

{

{ErrorHandler}, // Channel 09 - Reserved

{ErrorHandler}, // Channel 0A - Reserved

{ErrorHandler}, // Channel 0B - Reserved

{ErrorHandler}, // Channel 0C - Reserved

{ErrorHandler}, // Channel 0D - Reserved

{ErrorHandler}, // Channel 0E - Reserved

{ErrorHandler}, // Channel 0F - Reserved

{ErrorHandler}, // Channel 10 - Reserved

{ErrorHandler}, // Channel 11 - Reserved

{ErrorHandler}, // Channel 12 - Reserved

{ErrorHandler}, // Channel 13 - Reserved

{ErrorHandler}, // Channel 14 - Reserved

{ErrorHandler}, // Channel 15 - Reserved

{ErrorHandler}, // Channel 16 - Reserved

{ErrorHandler}, // Channel 17 - Reserved

{ErrorHandler}, // Channel 18 - Reserved

{ErrorHandler}, // Channel 19 - Reserved

{ErrorHandler}, // Channel 1A - Reserved

{ErrorHandler}, // Channel 1B - Reserved

{ErrorHandler}, // Channel 1C - Reserved

{ErrorHandler}, // Channel 1D - Reserved

{ErrorHandler}, // Channel 1E - Reserved

{ErrorHandler}, // Channel 1F - Reserved

{ErrorHandler}, // Channel 20 - Reserved

{ErrorHandler}, // Channel 21 - Reserved

{ErrorHandler}, // Channel 22 - Reserved

{ErrorHandler}, // Channel 23 - Reserved

{ErrorHandler}, // Channel 24 - Reserved

{ErrorHandler}, // Channel 25 - Reserved

{ErrorHandler}, // Channel 26 - Reserved

{ErrorHandler}, // Channel 27 - Reserved

{ErrorHandler}, // Channel 28 - Reserved

{ErrorHandler}, // Channel 29 - Reserved

{ErrorHandler}, // Channel 2A - Reserved

{ErrorHandler}, // Channel 2B - Reserved

{ErrorHandler}, // Channel 2C - Reserved

{ErrorHandler}, // Channel 2D - Reserved

{ErrorHandler}, // Channel 2E - Reserved

{ErrorHandler}, // Channel 2F - Reserved

{ErrorHandler}, // Channel 30 - XSRAM20K Access Violation

{ErrorHandler}, // Channel 31 - XGATE Software Error Interrupt

{ErrorHandler}, // Channel 32 - XGATE Software Trigger 7

{ErrorHandler}, // Channel 33 - XGATE Software Trigger 6

{ErrorHandler}, // Channel 34 - XGATE Software Trigger 5

{ErrorHandler}, // Channel 35 - XGATE Software Trigger 4

{ErrorHandler}, // Channel 36 - XGATE Software Trigger 3

{ErrorHandler}, // Channel 37 - XGATE Software Trigger 2

{ErrorHandler}, // Channel 38 - XGATE Software Trigger 1

{PWM_Init_Handler}, // Channel 39 - XGATE Software Trigger 0

{ErrorHandler}, // Channel 3A - Periodic Interrupt Timer

{ErrorHandler}, // Channel 3B - Periodic Interrupt Timer

{ErrorHandler}, // Channel 3C - Periodic Interrupt Timer

{ErrorHandler}, // Channel 3D - Periodic Interrupt Timer

{ErrorHandler}, // Channel 3E - Reserved

{ErrorHandler}, // Channel 3F - Autonomous Periodical interrupt API

{ErrorHandler}, // Channel 40 - Low Voltage interrupt LVI

{ErrorHandler}, // Channel 41 - IIC1 Bus

{ErrorHandler}, // Channel 42 - SCI5

{ErrorHandler}, // Channel 43 - SCI4

{ErrorHandler}, // Channel 44 - SCI3

{ErrorHandler}, // Channel 45 - SCI2

{ErrorHandler}, // Channel 46 - PWM Emergency Shutdown

{ErrorHandler}, // Channel 47 - Port P Interrupt

{ErrorHandler}, // Channel 48 - CAN4 transmit

{ErrorHandler}, // Channel 49 - CAN4 receive

{ErrorHandler}, // Channel 4A - CAN4 errors

{ErrorHandler}, // Channel 4B - CAN4 wake-up

{ErrorHandler}, // Channel 4C - CAN3 transmit

{ErrorHandler}, // Channel 4D - CAN3 receive

{ErrorHandler}, // Channel 4E - CAN3 errors

{ErrorHandler}, // Channel 4F - CAN3 wake-up

{ErrorHandler}, // Channel 50 - CAN2 transmit

{ErrorHandler}, // Channel 51 - CAN2 receive

{ErrorHandler}, // Channel 52 - CAN2 errors

{ErrorHandler}, // Channel 53 - CAN2 wake-up

{ErrorHandler}, // Channel 54 - CAN1 transmit

{ErrorHandler}, // Channel 55 - CAN1 receive

{ErrorHandler}, // Channel 56 - CAN1 errors

{ErrorHandler}, // Channel 57 - CAN1 wake-up

{ErrorHandler}, // Channel 58 - CAN0 transmit

{ErrorHandler}, // Channel 59 - CAN0 receive

{ErrorHandler}, // Channel 5A - CAN0 errors

{ErrorHandler}, // Channel 5B - CAN0 wake-up

{ErrorHandler}, // Channel 5C - FLASH

{ErrorHandler}, // Channel 5D - EEPROM

{ErrorHandler}, // Channel 5E - SPI2

{ErrorHandler}, // Channel 5F - SPI1

{ErrorHandler}, // Channel 60 - IIC0 Bus

{ErrorHandler}, // Channel 61 - Reserved

{ErrorHandler}, // Channel 62 - CRG Self Clock Mode

{ErrorHandler}, // Channel 63 - CRG PLL lock

{ErrorHandler}, // Channel 64 - Pulse Accumulator B Overflow

{ErrorHandler}, // Channel 65 - Modulus Down Counter underflow

{ErrorHandler}, // Channel 66 - Port H

{ErrorHandler}, // Channel 67 - Port J

{ErrorHandler}, // Channel 68 - ATD1

{ErrorHandler}, // Channel 69 - ATD0

{ErrorHandler}, // Channel 6A - SCI1

{ErrorHandler}, // Channel 6B - SCI0

{ErrorHandler}, // Channel 6C - SPI0

{ErrorHandler}, // Channel 6D - Pulse accumulator input edge

{ErrorHandler}, // Channel 6E - Pulse accumulator A overflow

{ErrorHandler}, // Channel 6F - Enhanced Capture Timer overflow

{ErrorHandler}, // Channel 70 - Enhanced Capture Timer channel 7

{ErrorHandler}, // Channel 71 - Enhanced Capture Timer channel 6

{ErrorHandler}, // Channel 72 - Enhanced Capture Timer channel 5

{ErrorHandler}, // Channel 73 - Enhanced Capture Timer channel 4

{ErrorHandler}, // Channel 74 - Enhanced Capture Timer channel 3

{ErrorHandler}, // Channel 75 - Enhanced Capture Timer channel 2

{ErrorHandler}, // Channel 76 - Enhanced Capture Timer channel 1

{ErrorHandler}, // Channel 77 - Enhanced Capture Timer channel 0

{ErrorHandler}, // Channel 78 - Real Time Interrupt

{ErrorHandler}, // Channel 79 - IRQ

};

kef · ‎06-06-2013

Do you mean project wizard created project isn't working?

I moved the xgate vector table in the non banked section flash (Rom C000). It seems to be reasonable.

No, it is not reasonable. XGATE can't access what can access CPU12X as nonbanked flash. XGATE has access to 14kB of PPAGE=0xE0 and to whole PPAGE=0xE1. Also XGATE has access to all the registers and 32kB of on chip RAM.

It is not clear, did you move XGATE vectors to CPU12X C file? You shouldn't do this. XGATE vectors table entries are specified as addresses in XGATE address space. It is possible to define XGATE vectors table in CPU12X C file, but you need to convert each address so that it is properly defined and properly used by XGATE. So all XGATE code and XGATE vectors table should be defined in *.cxgate or *.axgate files. If you are going to have multiple *.cxgate files, then you have to not forget to include hidef.h in each of these files. It is required for proper code and data placement.

View solution in original post

kef · ‎06-06-2013

Do you mean project wizard created project isn't working?

I moved the xgate vector table in the non banked section flash (Rom C000). It seems to be reasonable.

No, it is not reasonable. XGATE can't access what can access CPU12X as nonbanked flash. XGATE has access to 14kB of PPAGE=0xE0 and to whole PPAGE=0xE1. Also XGATE has access to all the registers and 32kB of on chip RAM.

It is not clear, did you move XGATE vectors to CPU12X C file? You shouldn't do this. XGATE vectors table entries are specified as addresses in XGATE address space. It is possible to define XGATE vectors table in CPU12X C file, but you need to convert each address so that it is properly defined and properly used by XGATE. So all XGATE code and XGATE vectors table should be defined in *.cxgate or *.axgate files. If you are going to have multiple *.cxgate files, then you have to not forget to include hidef.h in each of these files. It is required for proper code and data placement.

Claudione · ‎06-06-2013

Ok Edward you are right.

I have just revisited the data sheet. I started too fast and I did a big mistake.

I was thinking like HCS12.

Now the vector table is in page E0 again and it works good finally.

No I'didn't move the vector table in the CPU12X C file but I changed improperly the segment in the prm file. I put it in C000 flash address.

The wizard works correctly because I rewrote the project, add my op system again but i left the xgate parts where they were.

Thanks for your answer.

Xgate on HCS12XEP100 demo board problems

Xgate on HCS12XEP100 demo board problems

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