XC68HC912B32

[Yuping]

Hi there,

Does anyone know how to calculate the execution cycle for XC68HC912?

I saw there are "access details" for each instruction from the CPU12 reference manual. I can understand some of them, like "I" is reading indirect pointer, "r" is 8-bit data read. But I'm confused with the sequence of these letters. I thought "P" and "O" were for fetching instructions, so I thought the access details should always begin with "P" or "O". But there are exceptions. For example, STAA, the access details for M68HC12 are:

STAA opr8a                 Pw

STAA opr16a              wOP

STAA oprx0_xysp          Pw

STAA oprx9,xysp        PwO

STAA oprx16,xysp      PwP

STAA [D,xysp]         PIfPw

STAA [oprx16,xysp]  PIPPw

Does anyone know which direction is the instruction execution going? From right to left or left to right? But either direction has some instructions with "w" first. "w" is 8-bit data write. Why is there a write before even fetching the instruction?

Thanks a lot in advance for any inputs!!

Yuping 

[kef]

To calculate bus cycles: a) executing from internal RAM that allows misaligned word fetches (I hope it so not only on 912D60, but also on 912B32) just calculate those letters, w, P etc. b) executing from internal flash misaligned data word fetch takes 2 bus cycles. Corresponding access letters should be adjusted, c) executing/reading data from external memory take into account bus width, wait states etc.

It may be way simplier to use CodeWarrior simulator. It is possible to adjust Access Details in simulator. Go to Simulator -> Configure... and for every RAM/ROM etc memory resource click on Access Details -> Set Up... . At least it is possible to specify bus width and waitstates, also misaligned access waitstates

Execution is going from the left to the right. CPU has instructions queue, so it is possible some code is fetched after instruction did what it was supposed to do.

[Yuping]

Hi Kef,

Thank you so much for your reply! I appreciate it!

For the last part you stated out, do you mean if there is an instruction (i.e., STAA) following a one byte instruction (i.e., PSHB), the opcode of "STAA" was fetched when the CPU was fetching "PSHB", so the CPU could do something about "STAA" before it fetches the operands?

But as in the reference manual, when determining the access details, you can not assume there are instructions before the one you are considering, so how could there be "w" in the first place?

Thanks,

Yuping 

[kef]

Good question. And I'm not sure I know valid answer.

Did you look at LDAA details? It can be for example rPO. Looks like instruction is queued and ready to do its task in first instruction cycle. Interesting, isn't it? 

Now STAA with its PwP. i think second P cycle fills the queue with opcode of instruction that follows after STAA.

How rPO may work? If you look for example at conditional branches details, you may notice that conditional branches take single cycle when not taken and 3 when taken. 3 cycles should be enough to fill the queue...

[Yuping]

Hi Kef,

So the sequence of access details does not matter? They are just some possible combinations？

Thanks！

Yuping 

[kef]

Sorry, but I don't understand your question.

It is known how many CPU cycles (not the same like bus cycles) each instruction takes. PwP - stands for 3 CPU cycles. Executing from internal memories, most CPU cycles take single bus clock. Misaligned word R-ead or W-rite CPU cycle from/to internal fash takes 2 bus cycles.

It is known that STAA oprx9,xysp takes 3 CPU cycles, PwP. Both P-cycles stand for Program word fetch. It is not necessary that both P cycles are reading current instruction (STAA oprx9,xysp) opcodes. Since 'w' is in the middle, all 4 STAA oprx9,xysp instruction bytes are read before 'w' cycle. Of course one P cycle is not enough to read 4 bytes. Some bytes must be read while executing previous instructions.

[Yuping]

Hi Kef,

Sorry for the confusion...

By saying "the sequence of the access detail", I meant the order of the letters, like whether "P" is the first letter or "w" is the first letter does not indicate that when executing the instruction, the CPU fetches program information before it writes some memory or vice versa? Only in a complete program you would consider which one should come before others?

Say if you have "STAA opr16a" in your program, and the CPU has not fetched its object code when it's time to execute this instruction, then the access detail when the execution queue advances should be "PwO" instead of "wOP"?

Thanks,

Yuping 

[kef]

No, order of CPU cycles in instruction doesn't change, it is always the same.

PwO can't change to wOP. Like I said previously, branches always refil the queue! If specific addressing mode STAA CPU cycles are PwO, then STAA execution will start from P cycle, then w, and finally O, no other variants.

[Yuping]

Hi Kef,

Thanks a lot for the explanation! The access detail seems much clearer to me now.

The only question left is why could "w" always come before "P" in that case. What is the CPU writing when the program has not been fetched yet?

Thanks,

Yuping 

Message Edited by Yuping on 2009-10-29 06:39 PM

[kef]

'P' that comes after 'w' in STAA instruction fills instruction queue. Just fills instruction queue, of course with information from instruction(s) that come(s) after STAA. On 'w' CPU writes A to target memory location. Target address is already known. It must be known.

[Yuping]

So speaking about "access detail", you assume that the object code of current instruction is already in the queue?

But for other instructions has "P" at the first place. How do you know that you have to fill the queue before writing to memory?

[kef]

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Yuping wrote:

So speaking about "access detail", you assume that the object code of current instruction is already in the queue?

Not at all. I think that not later than at the start of w-cycle STAA instruction and its argument should be already decoded and ready to 'w'. I don't know is first P cycle used to fetch part of current STAA instruction or to fetch part of instruction after STAA. I only can assume that 'w' cycle couldn't be possible without known destination address.