Tomar - is it necessary to add external diode at RESET pin to VDDX?

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Tomar - is it necessary to add external diode at RESET pin to VDDX?

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2,976 次查看
cthhk
NXP Employee
NXP Employee

Dear Team:

 

We are using S12VR and we are reviewing the hardware design with OEM team.

In our application we use a pull-up resistor (4.7K Ohm) to VDDX and a pull-down cap (1nF) to GND at RESET pin.

 

The problem is, if the power (12V) was cut off, the cap would discharge to the resisitor which would cause a high voltage at the pin during a short time (maybe t = R * C), however at that time the internal circuit would drop to low, therefore do you see any risk of this temporary "short circuit"?

 

So we are considering to add an external discharging diode at RESET pin to VDDX in order to avoid this situation. Please share your thought.

 

And we also have a big cap (680uF) at VSUP in case of emergency, but not sure if it helps here.

 

Appreciate your support!

 

Best Regards,

Wang

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2,584 次查看
RadekS
NXP Employee
NXP Employee

Hi,

It is not necessary, but it is recommended.

BTW: S12VR has internal approximately 5KOhm pull-up. So, you don’t need external pull-up.

On other side, RESET pin (as also other pins) is protected by ESD diodes to VDDX. So, 1nF capacitance will be discharged to VDDX trough internal ESD diode. See Figure A-1. Current Injection on GPIO Port if Vin > VDDX in reference manual.

For long life of ESD diode (and MCU), injection current should be below 2.5mA. We can say that temporary (for short time) it will survive 25mA.

So theoretically you can use just resistor instead of diode for limiting discharging current (not recommended solution).

External diode between RESET pin and pull-down cap has additional main benefit. This will cause that capacitor will not be discharged during system reset and COP, CM resets could be safely recognized without taking capacitor capacitance into account.


I hope it helps you.

Have a great day,
RadekS

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2,585 次查看
RadekS
NXP Employee
NXP Employee

Hi,

It is not necessary, but it is recommended.

BTW: S12VR has internal approximately 5KOhm pull-up. So, you don’t need external pull-up.

On other side, RESET pin (as also other pins) is protected by ESD diodes to VDDX. So, 1nF capacitance will be discharged to VDDX trough internal ESD diode. See Figure A-1. Current Injection on GPIO Port if Vin > VDDX in reference manual.

For long life of ESD diode (and MCU), injection current should be below 2.5mA. We can say that temporary (for short time) it will survive 25mA.

So theoretically you can use just resistor instead of diode for limiting discharging current (not recommended solution).

External diode between RESET pin and pull-down cap has additional main benefit. This will cause that capacitor will not be discharged during system reset and COP, CM resets could be safely recognized without taking capacitor capacitance into account.


I hope it helps you.

Have a great day,
RadekS

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

2,584 次查看
cthhk
NXP Employee
NXP Employee

Hello Radek:

I have a further question that, the internal pull-up resistor at RESET pin is characterized as 3.8~10.5 kOhm and typically 5 kOhm.

Then if this internal pull-up and an external pull-down cap (1nF) are being used, will the reset timing and vector fetched (as described in Table 4-30. Reset Vector Selection) be affected?

Thanks and have a nice day.

Best Regards,

Wang

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2,584 次查看
RadekS
NXP Employee
NXP Employee

Hi,

Yes, 1nF should be fine for recognition between COP/CM resets and external reset under typical conditions (with 5kOhm pull-up).

Time constant in this case (1nF, 5kOhm) is 5us.

For detecting COP/CM reset it is necessary that voltage level at RESET pin achieve high level during 256 PLLCLK cycles after RESET pin release. After reset, PLLCLK value could be somewhere between 8 and 25MHz. If we take worst case with 25MHz PLLCLK, 256 PLLCLK cycles presents 10.24us.

However in worst case when Reset pull-up is 10.5kOhm, time constant with 1nF is 10.5us. This is already on the edge. Of course, it is still just combination of two worst case situations. We can add there also more variables (like pin capacitance (few pF), capacitor tolerance,…) and we will probably get even worse results.

However I would like to note that this situation could cause any problem only in case when we use different startup routines for COP/CM reset vectors than standard POR/External reset vector. Typically all three reset vectors points to the same startup routine.

Some more details about this topic could be found for example here:

https://community.freescale.com/docs/DOC-103737


I hope it helps you.

Have a great day,
RadekS

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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2,584 次查看
cthhk
NXP Employee
NXP Employee

Hi Radek:

Thank you for your analyze.

I prefer to use an external pull-up resistor of 4.7k Ohm now, so that the total resistance will be internal pull device || 4.7k, which will be less than 4.7k...

Do we have other recommended resistor value?

And is this why we always use 4.7k pull-up on all S12 evaluation board?

Best Regards,

Wang

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RadekS
NXP Employee
NXP Employee

Hi Wang,

According S12VR64EVB schematic, external pull-up has 10kOhm and 100nF capacitor. This give us time constant in hundreds us. I suppose that designer of this board didn't take into account COP/CM reset source recognize requirements (this is omitted in most of Freescale S12 evaluation boards). Anyway, you can anytime disassembly capacitor at RESET line. After that COP/CM reset source recognize will work correctly.

BTW: S12VR64EVB-3 (latest version) schematic has assembled 1kOhm resistor and ORANGE LED instead of external pull-up and no external capacitor at RESET line.

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2,584 次查看
cthhk
NXP Employee
NXP Employee

Dear Radek:

Very clear and thank you very much!

Best Regards,

Wang

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iggi
NXP Employee
NXP Employee

Yes, you can add a diode to the Reset circuitry.

Please see Figure 2. Reset circuit in the following appnote:

AN4643, S12VR Hardware Design Guidelines - Application Notes

Regards,

iggi

2,584 次查看
cthhk
NXP Employee
NXP Employee

Dear Iggi:

Got it and thank you very much! :smileyhappy:

Best Regards,

Wang

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