Hi,
Yes, 1nF should be fine for recognition between COP/CM resets and external reset under typical conditions (with 5kOhm pull-up).
Time constant in this case (1nF, 5kOhm) is 5us.
For detecting COP/CM reset it is necessary that voltage level at RESET pin achieve high level during 256 PLLCLK cycles after RESET pin release. After reset, PLLCLK value could be somewhere between 8 and 25MHz. If we take worst case with 25MHz PLLCLK, 256 PLLCLK cycles presents 10.24us.
However in worst case when Reset pull-up is 10.5kOhm, time constant with 1nF is 10.5us. This is already on the edge. Of course, it is still just combination of two worst case situations. We can add there also more variables (like pin capacitance (few pF), capacitor tolerance,…) and we will probably get even worse results.
However I would like to note that this situation could cause any problem only in case when we use different startup routines for COP/CM reset vectors than standard POR/External reset vector. Typically all three reset vectors points to the same startup routine.
Some more details about this topic could be found for example here:
https://community.freescale.com/docs/DOC-103737
I hope it helps you.
Have a great day,
RadekS
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