Stack Handling on XGATE Exit?

[mac164]

INTERRUPT STACK HANDLING:

I have developed an XGATE SCI(0) Handler. However I am confused about What & How the Interrupt is terminated on exit from XGATE. The Normal Exit of an XGATE Procedure is RTS (RTI is not accepted). With a S9-CPU ISR an RTI re-adjusts the stack and removes the INT from the Interrupt Controller.

1. The Ref manual seems to indicate that the proper procedure is (when exiting from XGATE) is to Interrupt the CPU which would generate an RTI to terminate the INT. I would not wish to do this. Is this the Case?

2. Does the INT Controller properly terminate the Interrupt when the XGATE exits on a RTS?

3. Will the Stack Overflow if the CPU does not issue a RTI ?

SHARED ARBITRATION:

It is clear that the CPU has priority over the XGATE and according to the Ref Manual XGATE is 'helded up' (put on hold) until the CPU releases the 'ADDRESS'. Disregarding the SEMAPHORE functions, What does ADDRESS mean.

1. Is it literally each word address? (i.e. the CPU can address $1002 and the XGATE can address $1004 at the same time).

2. If 1 above is not true, what is the Limits of the arbitration scheme.

3. Can anyone referenece a document or explain the speicifics of device arbitration?

Thank You

Mac

[HSW]

Mac,

which reference manual are you referring to? The MC9S12XEP100 reference manual does not contain any of your "pigeon English" quotes. Are you referring to the CodeWarrior documentation?

The S12XEP100's arbitration scheme is explained in section 3.4.4 (page 217) of the reference manual. Whenever two bus masters (CPU, XGATE, or BDM) access the same memory (target bus), the accesses are prioritized as listed in section 3.4.4.1 (page 218). The bus master with the lower priority will have to wait.

There are two things to keep in mind:

1. The XGATE is capable of accessing the RAM at twice the bus clock frequency (<=100MHz), whereas the CPU accesses the RAM at bus clock speed (<=50MHz). So even if the CPU continuously accesses the RAM, it does not stall XGATE RAM accesses. The XGATE is then still able to do one RAM access per bus clock cycle.
   This also means that CPU and XGATE can access the same RAM address within the same bus clock cycle.
2. CPU and XGATE can access the flash in parrallel as long as they access different flash blocks. On the S12XEP100, the flash block that is accessible from the XGATE is mapped to the address range $78_0000 to $79_FFFF. As long as the CPU doesn't read from this range, it does not interfere with the XGATE's program execution.

[GordonD · Accepted solution]

Mac,

XGate does not have a hardware stack pointer. By convention, register R7 is used as a software stack pointer. So if you want local variables or want to jump to a subroutine from the initial XGate ISR, you must manage the software stack your self. Note that in C the compiler takes care of this automatically. However, when writing in assembly, if you have no local variables and do not call subroutines, register R7 can be used like any other of the general purpose registers.

All that is needed to terminate an XGate thread (ISR) is the RTS (ReTurn to Scheduler) instruction.

With regard to you other questions, I hope my previous post (How to setup Xgate for Interrupt processing) answered these questions.

Regards,

Gordon