Safety mechanism for clock Failure : Stuck-at on gate level

cancel
Showing results for 
Search instead for 
Did you mean: 

Safety mechanism for clock Failure : Stuck-at on gate level

137 Views
premchand_chenn
Contributor I

Hello ALL

good day 

we are using S12ZVL128 IC. i have received FMEDA for S12ZVL128 IC

i have doubt   in Clock_FMEDA_VL128_CUSTOMER sheet 

Failure : Stuck-at on gate level 

the following SMs are suggested 

PLL Lock Interrupt used
[SM_0035]
[SM_1017]
[SM_0028] having a controlled diagnostic coverage of 60.0% and having a detected diagnostic coverage of 60.0%
Window COP Mode
[SM_1021] having a controlled diagnostic coverage of 90.0% and having a detected diagnostic coverage of 90.0%
Read back Clock configuration register within fault tolerant time interval
[SM_1030] having a controlled diagnostic coverage of 50.0% and having a detected diagnostic coverage of 50.0%
COP and COP Reset enabled
[SM_1020]
[SM_0028] having a controlled diagnostic coverage of 60.0% and having a detected diagnostic coverage of 60.0%

Question

for above failure(Stuck-at on gate level) we have implemented the SM =Window COP Mode
[SM_1021] having a controlled diagnostic coverage of 90.0% and having a detected diagnostic coverage of 90.0% 

this SM is enough to meet coverage 90% ?? or we need implement all SMs which are suggested for above failure ???  

Labels (1)
Tags (1)
0 Kudos
1 Reply

49 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello premchand.chennupati@valeo.com,

Please post this question in the SafeAssure NDA community group:
SafeAssure NDA group 

You would need to have an NDA first:
https://community.nxp.com/docs/DOC-335524 

Thank you,

Regards,

Daniel

0 Kudos