SPI slave configurations

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SPI slave configurations

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desponia_
Contributor I
Hi
 
i m developing codes to communicating by using SPI module in MC9S12DG128 microcontroller.
 
But i could not understand when and how i will write some value which i want to transmit to Master into the spi slave data register.
 
could you say me any way or send me any application?
 
best regards.
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desponia_
Contributor I

Dear Mac

 

you are so nice to reply me very well. Thanks a lot

as you said i will try to change slave SPIDR within the interrupt subroutine. For example if i take at the beginning slave SPIDR will  have S value. And when the master sends the M value it will take S from slave. and within the slave receive interrupt subroutine i will write SPIDR L value immediatly after reading SPIDR which has M value.

but if you have any application example for salve it would be better to have.

best regars.

 

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imajeff
Contributor III
Good question, the answer is probably simpler than you want :smileyhappy:

Master device is just that... the master. Slave devices are just that... slaves. They do not decide to transmit something to the master whenever they want.

When the master wants date from a slave, they have to send something to get something back. Often that means you send a "dummy" byte because you don't have anything else to give to the slave, but you want to read what it sends back.

This example would show how the master gets a 1-byte value from the slave after requesting address 0x103f:
Master  10 3F 00
Slave   00 00 33


When the slave is receiving the addr 0x103f to see what the master wants, it is returning dummy 0's. Then, when the slave returns 0x33 as the response, it won't be clocked out until the master sends a dummy.
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desponia_
Contributor I
Hi
 
my slave device is also a microcontroller. there is no adress where the master want to information . only the values will be send.
 
For instance lets speak about your example.
 
The master will send 10, 3F,00 and slave will take these
 
And the slave will send 00,00,33 and the master will take these
 
now please figure out my question now;
 
the master enables to communication and it can write 3 informations such as 10,3F,00 with in turn into the SPIDR register. But my question is that when the master write 10 to SPIDR it will shift out immediatly and the master will take 00 information which was in slave SPIDR. 1) how and when you are going to write this information into the slave SPIDR? and second  When master spi send 3F information how will you send second 00 information from the slave?
that is you must write 00 information into the slave SPIDR before the master writes 3F into the its SPIDR. and the same thing is  for the third information; the slave must write 33 into the its SPIDR before the master spi writes 00 into the its data register. How slave spi will do this?
 
for my codes; i want to send these information that 'M','A','S','T','E','R' from master to slave. And these  'S','L','A','V','E','00', are from slave to master. could you say me any way? 
 
and my configuration is the following shape;
 
MOSI is connected to MOSI
MISO is connected to MISO
SCK is connected to SCK
SS is connected to Vcc=5V on master side
and SS is connected to gnd=0V on slave side
 
are these connections true?
 
 
 
any algorithm?
 
best regards.
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bigmac
Specialist III

Hello Serkan,

Yes, you are correct - the slave send data must be written to the SPI send buffer prior to the next interrogation by the master.  So, when the slave SPI send buffer empties, the next send byte would be written, ready for a further transaction. 

In many cases, this process for the slave is best handled within an ISR for the SPI, depending on the amount of data to be sent by the slave.  Using a FIFO buffer would allow the ISR to automatically load the next available byte to the SPI send buffer.

"The master will send 10, 3F,00 and slave will take these
And the slave will send 00,00,33 and the master will take these"
If it is assumed that the slave is expected to respond with 0x33 after the master has sent 0x10, 0x3F as a "command" - a typical situation - and that the 0x00 are "dummy" bytes, here would be the sequence of events -
  1. Slave puts 0x00 in its send buffer (null data), ready for next transaction by master.
  2. Master sends 0x10 and receives 0x00.
  3. Slave receives 0x10 and puts 0x00 in send buffer (or does nothing).
  4. Master sends 0x3F and receives 0x00.
  5. Slave receives 0x3F, and determines that it needs to return 0x33,  so puts this value in send buffer.
  6. Master sends 0x00 (dummy), and receives 0x33.
  7. Slave receives 0x00, and puts 0x00 in send buffer.
"for my codes; i want to send these information that 'M','A','S','T','E','R' from master to slave. And these  'S','L','A','V','E','00', are from slave to master. could you say me any way?" 
  • Slave puts 'S' in its send buffer ready for next transaction by master.
  • Master sends 'M' and receives 'S'.
  • Slave receives 'M' and puts 'L' in send buffer.
  • Master sends 'A' and receives 'L'.
... and so on.
"MOSI is connected to MOSI
MISO is connected to MISO
SCK is connected to SCK
SS is connected to Vcc=5V on master side
and SS is connected to gnd=0V on slave side
 
are these connections true?"
You are basically correct, provided there is a single slave device, and you operate with SPI parameter CPHA = 1.  If CPHA = 0, the master will need to raise slave /SS input high after each transfer (this may be a GPIO line at the master, to control the slave /SS).  With more than one slave, the master device would need to provide a separate line to control each slave.
 
The code example given below is for the master and does not use interrupts.  It shows the method of monitoring the SPI flags.  The corresponding code for the slave would be more complex because of the ISR process and the provision of a FIFO buffer, and is not currently shown.
 
Making a few basic assumptions, suitable SPI initialisation values for the master might be -
 
SPICR1 = 0x54;
SPICR2 = 0x00;
 
You will also need to initialise SPIBR to a suitable value.  The following is a function to provide a master transaction -
 
byte SPI_proc (byte send_byte)
{
  while (!SPISR_SPTEF); /* Wait for Tx buffer empty */
  SPIDR = send_byte;
  while (!SPISR_SPIF);  /* Wait for Rx buffer full */
  return SPIDR;
}
 
For the three master operations in the example shown above, consider the following sequence -
 
SPI_proc(0x10);   /* Send first command byte & ignore return */
SPI_proc(0x3F);   /* Send second command byte & ignore return */
slave_val = SPI_proc(0); /* Send dummy byte & receive slave value */
 
Regards,
Mac
 

Message Edited by bigmac on 03-24-200608:52 PM

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