SPI SPIF flag not getting (Read) set in S12XDP512

[santhoshsl]

Hello All,

I am trying to interface an external SRAM from Microchip to S12XDP512 controller. And the interface is through SPI.

I am using SPI 1 of my controller for this purpose. The procedure to access this SRAM is straight forward. But I was not able to read data from the Device.

So I would like to get your help to review if my SPI read and Write are functions are correct. Please find the functions as below

void SPI1_Initialization(void)

{

   //initialize pins, mosi-0, sck/clr/ld/cs - 1

   SPI_MOSI = 1;

   SPI_MISO = 0;

   SPI_SCK = 1;

   SPI_CS = 1;

   SPI1BR = 0x07;//0x05;    //Clk rate=bus clock/256  , so Clk rate = 8000000/256 = 31250

   SPI1CR1 = 0x54;  // enable SPI, Master Mode,CPHA=1,CPOL=0, select clock polarity/phase

   SPI1CR2 = 0x00;     //Normal mode of operation

}

unsigned int SPI_Send(unsigned char Data)

{

unsigned int Test0;

    SPI_CS = 0;

    Test0 = SPI1DR;

    while( (unsigned char)(SPI1SR & 0x20) != 0x20); /* Wait SPTEF */

    SPI1DR = Data;                         //data stored in buffer and waiting for SCK

    SPI_CS = 1;

    return(1);

}

unsigned int SPI_Read(void)

{

   unsigned int temp_data, max_count, temp;

   max_count = 0xffff;

   SPI_CS = 0;

   while( ((unsigned char)(SPI1SR & 0x80) != 0x80) && (--max_count) ) ; // wait for End of Transmission

   temp_data = SPI1DR;

   SPI_CS = 1;

   return temp_data;

}

Can some one help me with this issue.

Thanks

Santhosh S L

[RadekS]

Few general notes abour SPI module:

We can say that all SPI devices typically work as simply shift register. If clock at SCLK pin is presented, data are transferred. SPI Master produce clock signal.

In fact there are two buffers behind SPIDR register in MCU. When you read SPIDR register, you always read receiver buffer. When you write to SPIDR register, you always write to transmitter buffer.

When MCU is master, write to SPIDR register also start SCLK signal generation.

Settings SPI1BR  = 0x00 (=fBUS/2) presents the maximum SCI speed for master mode. In slave mode is maximum communication speed fBUS/4. In fact, in slave mode have value of SPIBR no meaning, because baud rate divider is disabled to decrease IDD current.

There is example code for SPI read and SPI send:

#define SPIReadStatReg() (void)SPI0SR;  // Clear Status reg.

#define SPIReadDataReg() (void)SPI0DR;  // Clear Data reg.(Dummy read)

#define SPIWaitReceiveDone()        while (!(SPI0SR_SPIF)); // Wait for full buf 

#define SPIWaitTransferDone()       while (!(SPI0SR_SPTEF));//Wait for buf empty

/*******************************************************************************/

void SPI_send_byte(unsigned char data)

{

  SPIWaitTransferDone();      // Wait for buf empty

  SPIReadStatReg();           // Read status register (possible SPRF, SPTEF)  

  SPIReadDataReg();           // Read receive data register. It clears flags

  SPI0DR = data;              // Start transfer - send byte

  SPIWaitTransferDone();      // Wait for transfer complete

  SPIWaitReceiveDone();       // Wait for receive complete

}

/*******************************************************************************/

unsigned char SPI_read_byte()  

{

   unsigned char value=0;      // function cannot directly return register value

   SPIReadStatReg();           // Read status register (possible SPRF, SPTEF)  

   SPIReadDataReg();           // Read receive data register. It clears flags                 

   SPI0DR = 0x00;              // Generate clocks for reading 1 byte of data!

   SPIWaitReceiveDone();       // Wait for receive complete

   value = SPI0DRL;             // read received data and store to result 

   return(value);

}

[santhoshsl]

Hello Radek,

Thanks for your inputs. And infact I implemented my handlers in similar way.

But I am seeing some issues in seeing inconsistent behaviour with SPTEF and SPIF flags.

I feel, once the data is written in to the SPDR, SPTEF flag should be 0 for a while and then go back to 1. But in my debugging I could see that SPTEF flag being 1 always.

Similarly, when I send out a dummy data to initiate clock to read data from other device, I am  seeing SPIF going high when SPDR is loaded with value. But in the next line when i check for the SPIF flag like (while((SPI1SR& 0x80) != 0x80)), SPIF is going back to 0 and hence code getting stuck at this point.

I am not sure why this SPIF bit is being transient and I am not able to capture it with a logic operation.

Also when I try to initiate sck by writing dummy value on to the SPDR sometimes I am not seeing SCK on CRO. I am not sure why this SPI is being so inconsistent.

Can you please help me to resolve this issue.