S12ZVLA64 EMC CE TEST ISSUE

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S12ZVLA64 EMC CE TEST ISSUE

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Contributor II

Dear NXP Enginner:

       

     In our project, the NXP MCU S912ZVLA64F0MLF is used;

     At present stage, the EMC CE test failed,as below, the failure frequencies are  between the range of  31.8~35.8Mhz, and 96.2Mhz point;

Catch.jpg

We checked our design(circuit&programm) carefully, while no source of upper frequency points  were found.There are just MCU,SENSOR and CAN phy ,sensor and can phy just work in 500~900Khz frequence.schematic as below:

22.jpg

  

 

One doubt way is:

The DC regulator is internally intergated in the MCU (S912ZVLA64F0MLF) ;

Wheather  the upper relate  frequency are generated from the internal Regulator Block?

Besides,any other possible source of the relate  frequency?

It is urgent ,Could you help me ?thanks!

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Contributor I

刘先生您好!不知道您的CE问题解决了没有,我们现在也遇到了类似的问题,请问一下 ,您这边按照@Daniel Martynek 的方式解决了没有,以上的几种方式哪一个方式最有效果了,硬件方面我们改了pcb 增加了电容。是有效果但是还没有达到标准。

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Contributor II

Is there anyone can help answer my question.?thanks

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NXP TechSupport
NXP TechSupport

Hello,
I don't think this is caused by the regulator if you use the recommended decoupling capacitors.
Speaking of the regulator, if you use the external ballast transistor, the internal one must be disabled.
CPMUVREGCTL_INTXON = 0.

Have you tried changing the PLL/BUS clock frequency?
What is the frequency of the crystal?

Do you use the oscillator in Loop Controlled Mode or in Full-swing Mode?

The Full-swing mode offer higher immunity against noise injection on the cost of increased emission.

Please refer to AN5084 Hardware Design Guidelines for the S12ZVL Microcontrollers

3 Power management
5.2 Suggestions for the PCB layout of oscillator circuit
13 General Board Layout Guidelines
13.3 EMI/EMC and ESD Considerations for Layout

Regards,
Daniel