S12ZVL PLL configuration with CPMUPLL

[charudattaingal]

Hello Team,

Let us know appropriate place to configure CPMUPLL in clock configuration.

Currently we are using the given below configuration.

CPMUOSC_OSCE=0x01U; /* select external OSC. 10Mhz */

CPMUREFDIV_REFDIV=0x04U; /* select reference divider value */

CPMUREFDIV_REFFRQ=0x00U; /* select REFCLK frequency range Fref <= 2 Mhz */

CPMUSYNR_SYNDIV = 0x0FU; /* set VCO to 64 MHz (bus clock 32 MHz) */

CPMUSYNR_VCOFRQ = 0x01U; /* select VCOCLK frequency range 48Mhz < Fvco <= 64 Mhz */

CPMUPLL_FM0 = 0x1U;           /* Enable frequency modulation amplitude 4 % */
CPMUPLL_FM1 = 0x1U;

CPMUPOSTDIV_POSTDIV = 0x00U; /* PLL clock = 64 Mhz , divide by 2 (bus clock 32 MHz)*/

while (CPMUIFLG_LOCK == 0U){ /* To solve compiler warning { } added */ }; /* wait till PLL gets locked */

Is CPMUPLL configuration place appropriate. ?

Let us know if any suggestion to improve our clock configuration.

Thanks &  Regards,

Charudatta

[dianabatrlova]

Hello Charudatta,

If FM function is enabled it must be taken that maximum bus frequency is not exceeded.

The maximum bus clock frequency for the S12ZVL is 32 MHz. 

So, if you have the bus clock 32 MHz and FM is set at 4% you should consider that the bus clock frequency will be in the range 30.72 MHz - 33.28 MHz. So, in this case, we are not in the specified range.

So, the bus clock should be set less than 32 MHz when FM is enabled.

I hope it helps you.

Best Regards,

Diana

[charudattaingal]

Thanks Diana

Please let me know the Ideal bus clock values, when we configure/Enable FM  1, 2 and 4 %.

Are we configuring CPMUPLL at right place after configuring VCOCLK frequency?

Best Regards,

Charudatta

[dianabatrlova]

Hello Charudatta,

You can set the bus clock for example at 30 MHz after that the range with 4% FM will be 28.8 MHz - 31.2 MHz.

After that, we are in the specified range.

At first, I would like to recommend you to follow the steps in the RM rev2.47 below and after that, set the CPMUPLL register.

– Configure the PLL for desired bus frequency.
– Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if
necessary.
– Enable the external oscillator (OSCE bit).
– Wait for the oscillator to start up (UPOSC=1) and PLL to lock (LOCK=1).

if OSCE = 1        f_ref = f_osc / (REFDIV + 1) = 10MHz / (0 + 1) = 10MHz                    
                   f_vco = 2 * f_ref * (SYNDIV + 1) = 2 * 10MHz * (2 + 1) = 60MHz                                                   
      if LOCK = 1     f_pll = f_vco / (POSTDIV + 1) = 60MHz / (0 + 1) = 60MHz                        
                      f_bus = f_pll/2     = 30MHz

CPMUPOSTDIV = 0x00;   
// [4-0] POSTDIV = 0b00000   

CPMUSYNR = 0x42;  
// [7-6] VCOFRQ = 0b01 (48MHz < fVCO <= 64MHz)  
// [5-0] SYNDIV = 0b000010     

CPMUREFDIV = 0x80;  
// [7-6] REFFRQ = 0b10 (6MHz < fREF <= 12MHz)  
// [3-0] REFDIV = 0b0000        

CPMUIFLG = 0xFF;  // clear LOCKIF and OSCIF  
 
CPMUOSC_OSCE = 1;  // enable external oscillator OSCE   

// Wait for oscillator to start up (UPOSC=1) and PLL to lock (LOCK=1).
while (!CPMUIFLG_LOCK){}  
while (!CPMUIFLG_UPOSC){}  
 
CPMUCLKS_PLLSEL = 1;  
while(!CPMUCLKS_PLLSEL){}  
 
CPMUPLL = 0x30; // FM +-4%   
while (!CPMUIFLG_LOCK){}  
while (!CPMUIFLG_UPOSC){}

The MagniV PLL calculator can be useful if you want to calculate the value of PLL registers.

MagniV PLL Calculator 

I hope it helps.

Best Regards,

Diana