S12ZVC Reset state of GPIO pin(Port J)

[gilbertlee]

Hi!

Our customers want to verify the fail safety circuit in case of MCU failure.

If the voltage level of a port is measured, it is judged whether there is a failure.

In other words, to determine that the MCU has been damaged or that no SW has been written.

In case of erase the flash or use a MCU that has not been written anything, what we are wondering is what is the initial state of the port(GPIO).

Looking at Table 1-6 of the RM, there is reset state of each port. In case of PJ0, "Up" state.

I want to know the exact meaning of this "Up" state.

Question1. When the reset starts, how much voltage should be measured?

                  What is the size of the internal pullup resistor?

Question2. Out of reset, is this measured voltage level maintained? (Remember that there is no SW in the MCU).

According to our customer's measurements, when the reset starts, it is measured at 1.2 V for about 1.3 seconds, and then drops to 0V.         

[lama]

There are two types of reset - Power on and internal reset. The pictures are different device but the principle is the same. They are used only to better understand.

1) For power on reset; the value at the pin with pull up appears immediately after CMOS logic reaches its operating votage (app. 0.9V) from this moment the voltage at the pin is the same as an rising source voltage used for pin pull up device.

Measurement performed at the pin with pull up connected to the pin (in the data sheet it is presented as a pull up connected after reset)

Trigger is Vdd voltage

Procedure is: transformer plugged in mechanically, when I tried to use switch there were glitches - this power on is much better for image)

Blue: voltage at the pin with pull up defined after reset (log.0 written to the port after reset at 5.2ms)

Cyan: Vdd

Violet: reset pin voltage

2) For internal reset; the changes are performed immediately

Measurement performed at the pin with pull up connected to the pin (in the data sheet it is presented as a pull up

connected after reset) - the same as previous case

Trigger is falling edge at the reset pin - I have pressed the reset button

Vdd is constant

Blue: voltage at the pin with pull up defined after reset (log.0 written to the port after reset by SW)

Cyan: Vdd

Violet: reset pin voltage

Once more, these pictures are measured at different device. Not S12ZVC.

The table in the data sheet presents that the reset state of the pull resistor at the port J is pull-up.

The reset status of the registers PERJ1,0 is 0b11 which means pull device is enabled.

The reset status of the registers PPSJ1,0 is 0b00 which means pull-up device is connected to a pin. (you are able to recognize falling edges for interrupt)

The reset status of the registers DDRJ1,0 is 0b00 which means the port is set as an input - HiZ.(with pull up connected)

So the pin must by at logic level given by pull device except something is connected to it which pulls it down.

If there is no SW in the MCU then the behavior depends on the random content of the memory. I would be never sure the memory is erased so better is to test the device with defined program memory content.

The resistor is weak. It is created by mosfet structure and its value is not defined exactly. pull up = 20kohm~50kohm; Usually external stronger pull up resistors are required in applications  3.3k, 4.7k.

Best regards,

Ladislav

[gilbertlee]

Dear lama,

Sorry for late reply.

Thank you for your answer, It was very helpful for us.