S12Z - Simulating ECC errors at Flash by cumulative write

[#1]

This example simulates ECC issue by cumulative write into the same Flash area without an erasing.

The Flash erase operation set all bits into log1. The Flash program operation may keep bit cells in log1 state

or change it into log0 state, but not in opposite way.

The S12Z MCU Flash is protected by 39-Bit ECC Scheme. Every aligned 32bits is protected by additional 7 bits with ECC checksum.

The ECC values are not accessible for users.

Every Flash reading triggers also ECC check by internal logic. The single bit error in user data may be corrected by ECC checksum.

The double bit error cannot be corrected.

The ECC protection is implemented also at flash controller commands and results are signaling by MGSTAT bits.

The first case simulates Single-bit ECC error during reading. The MGSTAT bits after the second write are 0b10

due to fact that just 1 bit is different during write verification (correctable error)

The second case simulates Single-bit ECC error during reading. The MGSTAT bits after the second write are 0b11

due to fact that more than 1 bits are different during write verification (non-correctable error)

The third case simulates Double bit ECC error during reading. The MGSTAT bits after the second write are 0b11

due to fact that more than 1 bits are different during write verification (non-correctable error)

The flash patterns are selected for highlighted described behavior and they don't have any real meaning.

The cumulative write is not allowed for normal operation!!!

The code from this example should be used only for design testing - not in production!!!

Please, see the prm file. Address range 0xFF0000-0xFF01FF is excluded from default ROM and is used as user flash memory

The size of sectors is 512 bytes = 64 phrases.

Note: The PFLASH_Program() function was updated - erase verification is skipped

I hope it helps you.

Radek