S12XE's EBI performance

[jameshdx80]

Hi,

We are considering migrating our 15 years old design based on a S12 CPU to S12XE CPU. Unfortunately, around 5% of our code is very time sensitive. Before commit to this change, I am trying to infer what is going to happen. I have read the documentation and also have some hypothesis.

1. Since MC9S12DP512 (@50 MHz) has a bus at 25 MHz and MC9S12XEP100 (@50 MHZ) has a bus at 50 MHZ, a single instruction will run twice as fast?
I think the answer is yes. I know many other issues must be considered, but I am more interested in general terms such as a single NOP instruction.

2. In the best case scenario (highest performance), by using EBI on a MC9S12XEP100, I would have half of the internal

performance?

I think the answer is yes, again. If I run MC9S12XEP100 (@50 MHZ), even though the bus frequency would be 50 MHz, EBI minimum clock stretch is 1. Therefore, external bus is at 25 MHz. So broadly speaking, half of the internal performance. Of course I am assuming the fastest SRAM available (access time of 8 to 10 ns).

Thanks in advance.

James

[kef2 · Accepted solution]

Hi,

• 1. Since MC9S12DP512 (@50 MHz) has a bus at 25 MHz and MC9S12XEP100 (@50 MHZ) has a bus at 50 MHZ, a single instruction will run twice as fast?

Yes for "DP512  @50MHz has bus at 25MHz". XEP100 @100MHz has a bus at 50MHz. Oscillator (PLL) to bus clock ratio is the same for S12 and S12X, 1:2. Most or many of S12X instructions take the same amount of bus cycles like S12, some are faster. If you want to know which are faster then please get CPU12/CPU12X Reference Manual.

• 2. In the best case scenario (highest performance), by using EBI on a MC9S12XEP100, I would have half of the internal performance?

EBI speed is specified in A.7.3 of the XEP100 reference manual. 25MHz at 5V and 12.5MHz at 3.3V. Yes, fastest allowed internal bus clock is 2 to 4 times faster than fastest external bus clock.

Big advantage of S12X EBI is that you don't need

Edward 

[microdynamics]

Did you check the alternative of using port pins as Chip Enable, Read Enable, Write Enable, Address Latch Enable?

Using the port A as 8-bit register and/or ports A+B as 16-bit register for data / addresses as an example.

And then performing any memory access "by hand" using BSET and BCLR commands.

You are completely free.