S12XE TIM Input Capture Interrupt

[rayhall]

Hello,

This project is a traction controller that captures the injector pattern from an external engine management ECU. Then outputs the same pattern or blocks individual injector events based on the level of wheel slip.

I am using the TIM input capture to capture both rising and falling edges. I am not capturing the time between edges. I am using six channels. This all works perfectly on engines with sequential fuel injection.  When I tried it on a engine that starts in group fire then switches to sequential it causes loss of control during the group fire mode. In group file the engine management ECU is firing the injectors in three groups. This means two capture interrupts are occurring at the same time.  Below is just two of the interrupts. How do I get them to work correctly.

Ray.

//------------------------ TIM Input Capture Injector 3 Interrupt --------------------------------

#pragma CODE_SEG NON_BANKED

interrupt 87 void TIM0_INJ3_Isr(void)

{

   uint8_t pinState = PTIP_PTIP2;

   TIM_TFLG1 |= TIM_TFLG1_C2F_MASK; // Clear channel 2 flag

   PTT_PTT2 = (cal.tc.slipCutPattern[cal.data.cutLevel] >> 2) & pinState;

}

#pragma CODE_SEG DEFAULT

//------------------------ TIM Input Capture Injector 4 Interrupt --------------------------------

#pragma CODE_SEG NON_BANKED

interrupt 88 void TIM0_INJ4_Isr(void)

{

   uint8_t pinState = PTIP_PTIP3;

   TIM_TFLG1 |= TIM_TFLG1_C3F_MASK; // Clear channel 3 flag

   PTT_PTT3 = (cal.tc.slipCutPattern[cal.data.cutLevel] >> 3) & pinState;

}

#pragma CODE_SEG DEFAULT

[lama · Accepted solution]

You should keep in mind that instructions BSET or BCLR are read-modify-write. What does it mean?

Let flag register TFLG1 contains 0001 0001 and we want to clear bit 0 by means of instruction BSET for bit 0.

The result is that CPU reads 0001 0001, changes it to 0001 0001 and writes it back. It clears both interrupt flags because writing 0001 0001 back to the flag register will clear both flags.

In order to clear given bit(s) you have to write to the flag register mask which defines these bits. So, in previous case you have to write to the flag register number 0000 0001 in order to clear flag bit 0.

TFLG1 |= 0B00000001; // WRONG flag at bit 0 clearing -> clears all flags in TFLG1

TFLG1_C0F = 1; // WRONG flag at bit 0 clearing -> clears all flags in TFLG1 (BSET is used)

TFLG1 = 0B00000001; // CORRECT flag at bit 0 clearing -> clears flag at position 0 only

For more information please read Clearing and Disabling Interrupt Flags.pdf:

http://www.freescale.com/files/microcontrollers/doc/app_note/AN2554.pdf

Best regards,

Ladislav

[rayhall]

I will have to test this but it looks like TIM_TFLG1 &= ~ TIM_TFLG1_C0F; will leave bit 4 set and clear bit 1.

Ray.

[rayhall]

I have tested TIM_TFLG1 &= ~ TIM_TFLG1_C0F; and it is wrong.

Lama was correct.  The correct setting is TIM_TFLG1 =  TIM_TFLG1_C0F;

Ray.

[rayhall]

I am using TIM_TFLG1 |= TIM_TFLG1_C0F_MASK; // Clear channel 0 flag

If the CPU sets TIM_TFLG1 = 0B00010001 and on interrupt the above code then writes 0B00010001 to the register. It does not write 0B00000001

For it to write 0B00000001 to TIM_TFLG1, my code would need to be TIM_TFLG1 = TIM_TFLG1_C0F_MASK;

Ray.

[rayhall]

Lama,

Please do not mark my questions as answered until I have tested your reply. I have had many cases where answers are wrong. Also when you mark them as correct this closes the question and does not result in others offering a better solution.

Ray.