S12XE Oscillator Configuration Clarification

[stevenp]

I am relatively new to working with Freescale processors and in particular the S12XE processor and wanted to clarify some information about the oscillator setup. The two options I am considering are the Loop Controlled Pierce (LCP) and the Full Swing Pierce (FSP).

First, I would like to know which of the setups, LCP or FSP, is more immune to noise and disturbances? From what I have been able to find so far, it seems that the LCP is the better option, but I wanted to clarify this and see if there was further information on this choice. If that is the case, what then would be the benefit of the higher power FSP?

Second, I believe I have figured out how to configure the ~XCLKS pin (pin 24 of the 80-pin package). I believe that for LCP, pin 24 should be logic high. While for FSP, pin 24 should be logic low. Now the confusion comes in where in chapter 11 of the documentation (S12XE Clocks and Reset Generator) has the bit labeled XCLKS (not inverted) in the CLKSEL register. This bit is not inverted as it was in chapter 1 on the pin out and says a 0 is LCP and 1 is FSP. I want to clarify that pin 24 should be high for LCP and low for FSP, opposite of what the XCLKS bit says in the CLKSEL register.

[RadekS · Accepted solution]

Hi Steven,

Unfortunately it is hard to say what connection is better for more immune to noise and disturbances because there depends also on many other parameters like crystal parameters, PCB layout, Noise and Disturbance character,…

Therefore this has to decide for your application.

Generally we could say that LCP should be better from power consumption point of view and also signal radiation (EMI) could be lower.

I would like to recommend LCP. Many of our customers applied connection for FSP on their PCBs and they decide for one of connection on base of their EMC tests (simply assembly or do not assembly few resistors).

You are right, pin 24 (PE7) should be logic high for LCP mode and pin 24(PE7) should be logic low for FSP. Signals with inverted description as XCLKS, IRQ or RESET has inverted logic. It means that they are active low. CLKSEL register shows “not inverted” internal XCLKS signal (active high).

Correct XCLKS connection is described in chapter 1.13 Oscillator Configuration.

I hope it helps you.

Have a great day,
RadekS

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