S12X MSCAN Transmit buffer priority

[JohnBarber]

Hi,

I have a question regarding transmitting messages.

Consider the following scenario:

1. The priorities of the 3 TX buffers are set equal.

2. The 3 TX buffers are loaded with messages to be transmitted.

3. MSCAN starts to transmit the message in TX0 buffer.

4. When TX0 is transmitted a TX interrupt is raised and the ISR loads a new message to TX0.

5. Which message will be sent? TX0 or TX1?

I guess TX0 will be sent, is this correct?

Does this mean that the messages in TX1 and TX2 will not be sent as long we are loading new messages into TX0?

/John

[kef]

The question is what is the time between finish of previos transfer and next Tx buffer elections? I don't know if there's any gap. If there's no gap, then TX1 will be transferred. If there's at least 1 bit time gap, then at low bitrate and fast bus clock you may be quick enough to schedule TX0 before TX1 is selected.

[FIDDO]

How  to check the three transmit buffers in debugger!!

[RadekS]

By CANTFLG register you can check how many Tx buffers are available. For example:

CANTFLG=0x07 means that all three buffers are available.

CANTFLG=0x00 means that none of three buffers are available.

Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx bit is cleared and the buffer is scheduled for transmission.