S12X Chip Selects

[mcgeeph]

I'm looking at using the 9S12XDP512CAG.  While working out the connections for all of my peripherals, I realize that I'll need to make use of the IIC that is mux'd with CS0 & CS2.  My concern is, will this hamper my ability to use external RAM?  I've been looking through the datasheet and from what I can tell so far, it doesn't look like there should be any issues.  Though I would just like to make sure that neither chip select is special.  Thanks.

[Steve]

It depends on what you intend to do with the RAM.

CS0 maps to the "program space" of the MCU so memories controlled with this chip-select are usually extensions to the internal flash and are accessed through PPAGE.

CS2 maps to "extra EEPROM" and external space so access would be via EPAGE or GPAGE

Obviously if you intend to place the RAM in those spaces then the loss of the chip selects would make life more complicated. If you plan to place the RAM as an extension to the internal RAM then CS3 is the obvious choice.

The chip-selects are enabled under software control so if you don't need them then don't use them.

Have a look at AN2708 for an explanation on the low level operation of the interface.

[mcgeeph]

Thank you Steve. 

I was planning on using the RAM as an extention of the internal RAM.  Where is there a listing of specific functions for the different chip selects?  I must have missed that when I was looking. 

[Steve]

Have a look at the global memory map you'll see that the chip select ranges slot neatly into certain memory areas (XDP512 Data Sheet memory map section). This doesn't limit their use but it does indicate where they are most suited. The software implementation will usually be more straightforward if you use the chip selects as indicated.