S12G64 PLL Oscillator

[刘广扩]

hi,

I have a problem with PLL, follows are the program:

void PLL_Init(void)

{

CPMUOSC_OSCE = 1; /* enable ext osc */

/*

　　Initialise the system clock from a 16 MHz Crystal，

　　24 MHz Bus CLK （48 MHz VCO， 48 MHz PLL）

*/

CPMUSYNR = 0x00 | 0x05; /* VCOFRQ［7:6］， SYNDIV［5:0］ */

CPMUREFDIV = 0x00 | 0x03; /* REFFRQ［7:6］， REFDIV［3:0］ */

CPMUPOSTDIV = 0x00; /* POSTDIV = 0 FPLL = FVCO */

while(!CPMUFLG_LOCK); /* wait for VCO to stabilize*/

//Service_WD（）;

CPMUCLKS_PLLSEL = 1; /* Switch clk to use PLL */

}

It stops at "while(!CPMUFLG_LOCK); " , I have checked the value of REFDIV and SYNDIV, they are right the value programmed, and I have checked the EXTAL pin;

Is something wrong with my program? or something wrong with the hardware?

please help me ! amd sorry for my poor english!

[iggi]

Hi,

There seems to be problem with incorrectREFFRQ bit fields in the CPMUREFDIV register.

If fOSC=16MHz and  REFDIV is 3, then you get fREF=4MHz. In this case REFFRQ[1:0] = 01 (see Table 10-2. in the S12G ref manual), but you have it '00' there.

So it should be like this:

CPMUSYNR = 0x05;

CPMUREFDIV = 0x83;

CPMUPOSTDIV = 0x00;

In the main code you can use a codeline which will route the bus clock to the external pin ECLK, so you can check the signal on scope:

ECLKCTL_NECLK = 0;	// enable ECLK output (bus clock is visible on pin PB0 for TWR-S12G128, PS7 for TWR-S12GN32)
	// default clock setup after reset is PEI mode 6.25MHz BUSCLK

Also you can check appnote AN4455 which comes with the SW packt. There you can find Demo Labs such as the one demonstrating how to configure System Clocks.

http://cache.freescale.com/files/microcontrollers/doc/app_note/AN4455.pdf

http://cache.freescale.com/files/microcontrollers/doc/app_note/AN4455SW.zip

Regards,

iggi

[刘广扩]

Thanks for your reply, I have found why the PLL did not work.

I<mc9s12g family reference manual and data sheet> ,page 354

The Phase Locked Loop (PLL) has the following features:
• highly accurate and phase locked frequency multiplier
• Configurable internal filter for best stability and lock time.
• Frequency modulation for defined jitter and reduced emission
• Automatic frequency lock detector
• Interrupt request on entry or exit from locked condition
• Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based.
• PLL stability is sufficient for LIN communication, even if using IRC1M as reference clock

I changed the Oscillator to crystal, then the PLL works.