Hi,
You are asking a little too much. Detail instructions for something, which almost no one uses in its practice. Well, by now I have only S12XD board at hand, which has little different debug module. Perhaps later I'll try it on S12P, which should be more similar to S12G. By now only steps for S12XD:
Let’s start from simple thing, SWI handler to receive breakpoint event, blank for now, for(;;) loop to pause and make sure MCU lands in it
#pragma CODE_SEG __NEAR_SEG NON_BANKED
interrupt VectorNumber_Vswi void swiisr(void)
{
for(;;) { }
}
#pragma CODE_SEG DEFAULT
You should read carefully S12S Debug Module chapter in S12G datasheet. Should be quite similar to S12X. Let’s set up comparator B for S12XD
DBGC1 &= ~DBGC1_ARM_MASK; // unarm, make registers writeable
DBGC1 &= ~DBGC1_BDM_MASK; // choose SWI instead of BDM
DBGC1_DBGBRK = 2; // CPU12X breakpoints
DBGC1_COMRV = 1; // choose comparator B
DBGXCTL =
DBGXCTL_SZE_MASK * 0 // ignore compare size
| DBGXCTL_NDB_SZ_MASK * 0
| DBGXCTL_TAG_MASK *0 // TAG=1 are for code breakpoints, TAG=0 – data R/W breakpoints
| DBGXCTL_BRK_MASK *1 // immediate breakpoint
| DBGXCTL_RW_MASK *0 // match write cycle
| DBGXCTL_RWE_MASK *1 // R/W used in comparison
| DBGXCTL_SRC_MASK *0 // CPU
| DBGXCTL_COMPE_MASK*1; // enable comparator
DBGXAH = (unsigned long)&PUCR >> 16; // PUCR address
DBGXAM = (unsigned long)&PUCR >> 8;
DBGXAL = (unsigned long)&PUCR ;
DBGSCRX = 2; // any match triggers to final state
DBGC1 |= DBGC1_ARM_MASK; // arm module, required to enable breakpoint
Now you may wish to check it works, add some code to write PUCR,
PUCR=PUCR ; // or something like that
Once you enter debugger, you should go to HC12MultilinkCyclonePro->Trigger Module Settings.. and switch from Automatic to Disabled to stop debugger using debug module. Now you have debugger breakpoints broken, but working your “sudden PUCR overwrite” catcher.
Now one or more problems arise. If you are using preemptive RTOS, chances are SWI handler is used for RTOS purposes. You could then try reconfiguring your RTOS to use TRAP handler instead of SWI or perhaps add code to distinguish, was it your PUCR breakpoint or normal RTOS usage. On S12XD you can check for DBGC1_ARM bit in SWI handler. Occurrence of breakpoint seems reseting DBGC1_ARM bit.
Another thing you should consider misaligned word write to MODE@0xB, which will overwrite PUCR@0xC as well. You need to setup at least two breakpoints. One for byte/word write to 0xC (PUCR) and another one for word write to 0xB. At least on S12XD DBG module looks for destination address, not for matching aligned word address. What I see on S12XD, when address is odd, both byte and misaligned word write to given odd address trigger breakpoint, but don’t trigger doing aligned word write. The question is what about instructions like EMACS? EMACS writing 32bits to 0x9..0xC will overwrite PUCR, but will it trigger breakpoint? We need to check. If not, then you should setup address range compare breakpoint and consider all write hits to 0x9..0xC as potential PUCR overwrite events.
And the last thing is deducing PC location which triggered PUCR overwrite breakpoint. 16bit return address from SWI handler is at SP+7 for S12 and SP+8 for S12X. Don’t forget about possible stack frame.
Edward
