Regarding susequent PTU trigger timing difference in S12ZVML64

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Regarding susequent PTU trigger timing difference in S12ZVML64

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Contributor V

Dear Team,

I am referring the S12ZVM family datasheet "MC9S12ZVMRM_V2.13"

As per the note given on Page No. 80 of datasheet,

pratibhasurabhi_0-1602049502336.png

Subsequent trigger require a load time of 10bus clock cycle for both generators enabled.

So my understanding is, we can keep a difference of 10bus clock cycle in PTU trigger timing.

For the below clock setting we have tried the above mentioned difference but we are getting the trigger error. For below clock setting, If we keep a trigger difference of greater than 99 count will getting the ADC result without any error. but we are not getting how this value is correct?

fosc = 20MHZ

fcore(fpll) = 100MHz

fbus = 50MHz

fADC = 6.25MHz

We are sampling 3 signals on ADC 0 and one signal on ADC1.

So i want to know how to calculate the minimum ADC trigger value which will be used to set the next PTU trigger time

Example: For ADC0,

PTU Trigger[0] = duty cycle >>2;  //first trigger at half of duty cycle

PTU Trigger[1] = PTU Trigger[0] + MIN_ADC_TRIGGER; // Second trigger value

 

so what we should set the MIN_ADC_TRIGGER macro value to get the proper ADC result without any error?

Please request you to guide on this issue.

Thanks in advance.

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NXP TechSupport
NXP TechSupport

Hello Pratibha,

The delay between subsequent PTU triggers should be longer than the conversion time of the sequence that is triggered first.

danielmartynek_0-1602068988849.png

A single conversion time:

danielmartynek_1-1602069293749.png

After a trigger, it takes also 2 Bus Clock cycles and 2 ADC cycles until the sampling starts.

Please note that the Pump Phase mentioned below is the "Buffer" Sample Time in the Figure above.

danielmartynek_2-1602069676245.png

 

Regards,

Daniel

 

 

 

 

 

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