I am trying to generate one pulse PWM on low sides of all 3 phases.
Following is the chunk of relevant code
PMFCFG0_EDGEA = 1; /* Set Pair A PWM as edge aligned */
PMFCFG0_EDGEB = 1; /* Set Pair B PWM as edge aligned */
PMFCFG0_EDGEC = 1; /* Set Pair C PWM as edge aligned */
PMFCFG0_INDEPC = 1; /* Set pairs in independent mode */
PMFCFG0_INDEPB = 1;
PMFCFG0_INDEPA = 1;
PMFENCA_LDOKA = 1; /* Load prescalar A,modulus A and PMFVAL values into set of buffers */
PMFENCA_RSTRTA = 1; /* PWM will restart at commutation event */
PMFENCA_PWMENA = 1; /* Enable PWM Generator A */
PMFCFG1_ENCE = 1; /* Enable commutation event */
PMFENCA_GLDOKA = 1; /* External load OK replaces the function of LDOKA */
In the ADC0 conversion done ISR [falling at every 50usec], I have set the PMFCFG2 and OUTCTL according to my requirement of PWM output on all low side.
So for one iteration of the 50usec ISR it is execpected that PWM should be output on all low sides while for the next teration, they should be off.[ ie expecting 2 commutations where first LS PWM is output and after 50us LS are off ]
The commutation is forceful commutation[FOC0 =1]
The mask registers, OUTCTL, PMFVAL and PTULDOK are set in the same 50usec ISR
The ISR is delayed when the foreceful commutation is applied and after 50usec the same pattern of PWM output on low sides is visible. When the next cycle of 50usec falls, all LS are switched off.
Why does the ISR get delayed.
Is it due to forced commutation?
and what changes should be made to avoid this.
In the below image , rise and fall of ADC0done ISR indicates entry and exit.
It is observed that prior to pattern output, the ISR is periodic.
As soon as the pattern is output for the first time, the ISR is not found to occur and the previous pattern is ouput again.
The period between those two pattern is 50usec.
Please enable PTU signals on the PORTs so that you can see when exactly it gets reloaded and when the ADC is triggered.
When you are changing the duty-cycle of the PWM, the PTU triggers should be adjusted.
This is probably the reason why you see the delay.