Output compare on Freescale 9S12P64

[RA]

Hi,

Iam trying to generate 5 PWM signals using output compares, TC0-TC5,

The problem is the pulse width needed on those signals is very small (125 ns), and the period is 4us.

in addition, these PWMS has to be 0.5 us apart,

If the period and PWM were larger, I can use 4 isrs to generate them, since the period is too small (125ns), by the time the isr fires, it does not allow to generate this small duty (min it will be around 0.7us), i prefer not to use the ISRs if possible.

any suggestions

[kef]

I know only one TIM/ECT setup that could be used to generate such small PWM periods. In that setup TC7 defines common PWM period. TCRE must be set to reset TCNT at the end of PWM period. TCx (x!=7) defines period minus duty cycle time. OC7Dx and OC7Mx bits are used to define output compare edge at the end of PWM period. OLx Mx bits define polarity of another pwm edge. You can have up to 7 PWMs with common PWM period using such setup.