Modes of clock in MC9S12G128

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Modes of clock in MC9S12G128

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huuhuynhchi
Contributor III

Dear all,

 

As me known, Clock in MC9S12G128 has 3 modes operation which are PEI, PEE and PBE. But I don't know when we use each others and their usage ? If any one know, can share me know, please. Thank all

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RadekS
NXP Employee
NXP Employee

Hi Huu,

About typical usage:

PEI is default clock mode. Clock is based on internal 1MHz RC oscillator with 1% accuracy and result VCO/Bus clock is gated from PLL.

PEE mode – external crystal is used instead internal RC oscillator. We use this mode in case of necessary higher clock accuracy, like for CAN, time measurement,…

PBE mode – external crystal is used as VCO/Bus clock source, PLL is disabled. This mode could be used in case when we do not want use PLL like for very noisy environment, time critical applications…. This mode is not used very often. Bus clock range is here limited by oscillator range (max 8MHz bus clock).

Power consumption in run mode depends mainly on bus clock value.


I hope it helps you.

Have a great day,
RadekS

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EDIT: fixed typo error - switched PEE and PBE description.

View solution in original post

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1,755 Views
RadekS
NXP Employee
NXP Employee

Hi Huu,

About typical usage:

PEI is default clock mode. Clock is based on internal 1MHz RC oscillator with 1% accuracy and result VCO/Bus clock is gated from PLL.

PEE mode – external crystal is used instead internal RC oscillator. We use this mode in case of necessary higher clock accuracy, like for CAN, time measurement,…

PBE mode – external crystal is used as VCO/Bus clock source, PLL is disabled. This mode could be used in case when we do not want use PLL like for very noisy environment, time critical applications…. This mode is not used very often. Bus clock range is here limited by oscillator range (max 8MHz bus clock).

Power consumption in run mode depends mainly on bus clock value.


I hope it helps you.

Have a great day,
RadekS

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

EDIT: fixed typo error - switched PEE and PBE description.

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huuhuynhchi
Contributor III

Hi Radek,

Thank for your support. But I have a question about PEE mode, when I  read Reference Manual of MC9S12 which has a sentence "The Bus Clock is based on the PLLCLK". In your answer, Why the PLL is disable ? Can you explain for me understand clearly. Thank you very much.

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RadekS
NXP Employee
NXP Employee

Hi Huu,

I am so sorry, my fault.

I switched PEE and PBE descriptions.

It should be:

“PEE mode – external crystal is used instead internal RC oscillator. We use this mode in case of necessary higher clock accuracy, like for CAN, time measurement,…

PBE mode – external crystal is used as VCO/Bus clock source, PLL is disabled. …”

Best Regards

RadekS

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huuhuynhchi
Contributor III

Hi Radek,

You're welcome. Thank you :smileyhappy:

Your information is very useful for me.

Regrading to clock for MC9S12G, I also have another question. VCO Clock of MC9S12 default is 50MHz. Is this a fixed value or flexible value ? thank you very much.

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RadekS
NXP Employee
NXP Employee

Hi Huu,

VCO clock value is flexible. VCO locking range is 32-50MHz.

fVCO = 2 × fREF × (SYNDIV + 1)

According selected fVCO we should configure internal filter by CPMUSYNR_VCOFRQ bits.

The following rules help to achieve optimum stability and shortest lock time:

• Use lowest possible fVCO / fREF ratio (SYNDIV value).

• Use highest possible REFCLK frequency fREF.

You could use PLL calculator for calculating of clock registers configuration. Please run calculator from attachment and select S12P (it was first S12 family with CPMU module), Input clock frequency and requested bus clock. PLL calculator will give you directly values which have to be written into CPMUSYNR, CPMUREFDIV and CPMUPOSTDIV registers.

I hope it help you.

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huuhuynhchi
Contributor III

hi Radek,

Thank all things that you support for me...I also have an other question, Do you know Core Clok and Bus Clock in S12G ?What is Core Clock ? and When do we use Core Clock? Becuse I don't have more knowledge about this. Can you help me, please ? :smileyhappy:

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RadekS
NXP Employee
NXP Employee

No, problem.

In case of S12G, Bus clock is derived from Core clock by divider by 2: Bus clock=Core clock/2.

Core clock is equal to PLLCLK(PEI, PEE modes) or OSCCLK(PBE mode).

See Figure 10-1. Block diagram of S12CPMU in RM.

Since ratio between Bus and Core clock is constant, we typically use Bus Clock as value for all timing calculations.

Exception: System startup is described by 768(=512+256) PLLCLK cycles procedure. In this case PLLCLK = Core clock.

So, when we wrote that S12G could run up to 25MHz, we mean that bus clock could be up to 25MHz (Core clock up to 50MHz). Also instruction lengths are defined by number of bus clocks.

More details about S12 CPU core and instructions:

http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12CPUV2.pdf

or

http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12XCPUV2.pdf

I hope it helps you.

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huuhuynhchi
Contributor III

Hi Radek,

It is very useful :smileyhappy: thank you very much :smileyhappy:

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RadekS
NXP Employee
NXP Employee

In S12G Examples Pack​ are examples for all three modes.


I hope it helps you.

Have a great day,
RadekS

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