Message Edited by Alban on 02-28-2006 11:48 AM
The RTI period is based on the Xtal frequency directly and you have selected Fxtal/16384. But you have only mentioned the Fbus which is determined by the PLL setup in conjunction with the Fxtal.
P.S. This should probably have been a new subject in the 16 bit forum!
[Alban changed subject after moved thread to proper board]
Message Edited by Alban on 02-28-2006 11:49 AM
i m using in real time interrupt system clock which is driven by PLL. that is PLLCLK=SYSCLK=RTI main clock (see attachment please)
my PLL sysclk=12Mhz
then for RTICTL= 0x1F my ral time int period will be T= 1/[f/16384]
T= 1/ [12Mhz/16384] =1 / 732.421Hz = 1.365milisecond.
but i m seeing it on asciloscope screen as 4.1 milisecond. what is the problem.
The only time the RTI clock is derived from PLLCLK is when SCM is set. This is Self Clocked Mode which is meant to keep everything alive during clock loss. In SCM the PLLCLK runs at fSCM which is quoted in the electrical specs as 1-5.5MHz.
So if your measuring 4.1 ms period of RTI then this particular device has a fSCM of 3.996MHz (16384/0.0041). Well within spec!
From CRG manual:
SCM — Self Clock Mode Status Bit
SCM reflects the current clocking mode. Writes have no effect.
1 = MCU is operating in Self Clock Mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK running at its minimum frequency fSCM.
0 = MCU is operating normally with OSCCLK available.
From DG manual:
Rating Symbol Min Typ Max Unit
Self Clock Mode frequency fSCM 1 5.5 MHz